gpu: nvgpu: gr_priv header cleanup

Remove gr_priv.h from outside gr files.
Add hal function in gr.init for get_no_of_sm. This helps
to avoid dereferencing gr in couple of files for g->gr->config and
avoid gr_priv.h include in those files.

Replace nvgpu_gr_config_get_no_of_sm call with
g->ops.gr.init.get_no_of_sm for files outside gr unit.

Jira NVGPU-3218

Change-Id: I435bb233f70986e31fbfcb900ada3b3bda0bc787
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109182
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/tsg.c

@@ -34,8 +34,6 @@
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/runlist.h>
 
-#include "common/gr/gr_priv.h"
-
 void nvgpu_tsg_disable(struct tsg_gk20a *tsg)
 {
 	struct gk20a *g = tsg->g;
@@ -622,7 +620,7 @@ static struct tsg_gk20a *gk20a_tsg_acquire_unused_tsg(struct fifo_gk20a *f)
 
 int nvgpu_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg, pid_t pid)
 {
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(g->gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 	int err;
 
 	/* we need to allocate this after g->ops.gr.init_fs_state() since

drivers/gpu/nvgpu/common/gr/fs_state.c

@@ -99,12 +99,12 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
 		}
 
 		/* Is table empty ? */
-		if (nvgpu_gr_config_get_no_of_sm(config) == 0U) {
+		if (g->ops.gr.init.get_no_of_sm(g) == 0U) {
 			return -EINVAL;
 		}
 	}
 
-	for (sm_id = 0; sm_id < nvgpu_gr_config_get_no_of_sm(config);
+	for (sm_id = 0; sm_id < g->ops.gr.init.get_no_of_sm(g);
 	     sm_id++) {
 		struct sm_info *sm_info =
 			nvgpu_gr_config_get_sm_info(config, sm_id);

drivers/gpu/nvgpu/common/gr/gr.c

@@ -104,6 +104,11 @@ static int gr_alloc_global_ctx_buffers(struct gk20a *g)
 	return 0;
 }
 
+u32 nvgpu_gr_get_no_of_sm(struct gk20a *g)
+{
+	return nvgpu_gr_config_get_no_of_sm(g->gr->config);
+}
+
 u32 nvgpu_gr_gpc_offset(struct gk20a *g, u32 gpc)
 {
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -305,6 +305,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
 		.init = {
+			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
 			.fs_state = vgpu_gr_init_fs_state,
 			.get_bundle_cb_default_size =

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c

@@ -1102,7 +1102,7 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
 {
 	struct nvgpu_tsg_sm_error_state *sm_error_states;
 	struct tsg_gk20a *tsg;
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(g->gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 
 	if (info->sm_id >= no_of_sm) {
 		nvgpu_err(g, "invalid smd_id %d / %d", info->sm_id, no_of_sm);

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -355,6 +355,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
 		.init = {
+			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.get_nonpes_aware_tpc =
 					gv11b_gr_init_get_nonpes_aware_tpc,
 			.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b.c

@@ -26,7 +26,6 @@
 #include "gr_falcon_gp10b.h"
 #include "gr_falcon_gm20b.h"
 #include "common/gr/gr_falcon_priv.h"
-#include "common/gr/gr_priv.h"
 
 #include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 

drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c

@@ -1902,7 +1902,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
 	int err;
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
 	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(g->gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 
 	ops = nvgpu_kcalloc(g, no_of_sm, sizeof(*ops));
 	if (ops == NULL) {
@@ -2100,10 +2100,9 @@ int gr_gk20a_trigger_suspend(struct gk20a *g)
 int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
 {
 	int err = 0;
-	struct nvgpu_gr *gr = g->gr;
 	u32 gpc, tpc, sm, sm_id;
 	u32 global_mask;
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 
 	/* Wait for the SMs to reach full stop. This condition is:
 	 * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE)
@@ -2185,12 +2184,11 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g)
 
 u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
 {
-	struct nvgpu_gr *gr = g->gr;
 	u32 sm_id, tpc_exception_en = 0;
 	u32 offset, regval, tpc_offset, gpc_offset;
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
 	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 
 	for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
 		struct sm_info *sm_info =

drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c

@@ -506,7 +506,7 @@ void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
 	u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0;
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
 	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 
 	/* for maxwell & kepler */
 	u32 numSmPerTpc = 1;

drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c

@@ -1376,7 +1376,7 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
 	u32 gpc, tpc, sm, sm_id;
 	u32 offset;
 	u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0;
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 
 	for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
 		struct sm_info *sm_info =
@@ -1443,7 +1443,7 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
 {
 	struct nvgpu_dbg_reg_op *ops;
 	unsigned int i = 0, sm_id;
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(g->gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 	int err;
 
 	ops = nvgpu_kcalloc(g, no_of_sm, sizeof(*ops));

drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c

@@ -401,7 +401,7 @@ int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
 	u32 tpc_index, gpc_index, tpc_id;
 	u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
 	u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS);
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr_config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 
 	/* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/
 	for (i = 0U;

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -426,6 +426,7 @@ static const struct gpu_ops gm20b_ops = {
 			.program_zcull_mapping = gm20b_gr_program_zcull_mapping,
 		},
 		.init = {
+			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.wait_initialized = nvgpu_gr_wait_initialized,
 			.ecc_scrub_reg = NULL,
 			.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -473,6 +473,7 @@ static const struct gpu_ops gp10b_ops = {
 			.program_zcull_mapping = gm20b_gr_program_zcull_mapping,
 		},
 		.init = {
+			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.wait_initialized = nvgpu_gr_wait_initialized,
 			.ecc_scrub_reg = NULL,
 			.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,

drivers/gpu/nvgpu/hal/init/hal_gv100.c

@@ -607,6 +607,7 @@ static const struct gpu_ops gv100_ops = {
 				gv100_gr_hwpm_map_get_active_fbpa_mask,
 		},
 		.init = {
+			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.get_nonpes_aware_tpc =
 					gv11b_gr_init_get_nonpes_aware_tpc,
 			.wait_initialized = nvgpu_gr_wait_initialized,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -580,6 +580,7 @@ static const struct gpu_ops gv11b_ops = {
 				gv100_gr_hwpm_map_align_regs_perf_pma,
 		},
 		.init = {
+			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.get_nonpes_aware_tpc =
 					gv11b_gr_init_get_nonpes_aware_tpc,
 			.wait_initialized = nvgpu_gr_wait_initialized,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -637,6 +637,7 @@ static const struct gpu_ops tu104_ops = {
 				gv100_gr_hwpm_map_get_active_fbpa_mask,
 		},
 		.init = {
+			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.get_nonpes_aware_tpc =
 					gv11b_gr_init_get_nonpes_aware_tpc,
 			.wait_initialized = nvgpu_gr_wait_initialized,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -679,6 +679,7 @@ struct gpu_ops {
 		} hwpm_map;
 
 		struct {
+			u32 (*get_no_of_sm)(struct gk20a *g);
 			u32 (*get_nonpes_aware_tpc)(struct gk20a *g, u32 gpc,
 				u32 tpc, struct nvgpu_gr_config *gr_config);
 			void (*wait_initialized)(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/gr/gr.h

@@ -27,6 +27,7 @@
 
 struct gk20a;
 
+u32 nvgpu_gr_get_no_of_sm(struct gk20a *g);
 int nvgpu_gr_prepare_sw(struct gk20a *g);
 int nvgpu_gr_enable_hw(struct gk20a *g);
 int nvgpu_gr_reset(struct gk20a *g);

drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c

@@ -29,8 +29,6 @@
 #include <nvgpu/gr/fecs_trace.h>
 #include <nvgpu/string.h>
 
-#include "common/gr/gr_priv.h"
-
 #include "platform_gk20a.h"
 #include "os_linux.h"
 #include "fecs_trace_linux.h"

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -704,12 +704,13 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
 	struct nvgpu_warpstate *w_state = NULL;
 	u32 ioctl_size, size, sm_id, no_of_sm;
 
-	no_of_sm = nvgpu_gr_config_get_no_of_sm(g->gr->config);
+	no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 
 	ioctl_size = no_of_sm * sizeof(struct warpstate);
 	ioctl_w_state = nvgpu_kzalloc(g, ioctl_size);
-	if (!ioctl_w_state)
+	if (!ioctl_w_state) {
 		return -ENOMEM;
+	}
 
 	size = no_of_sm * sizeof(struct nvgpu_warpstate);
 	w_state = nvgpu_kzalloc(g, size);
@@ -719,8 +720,9 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
 	}
 
 	err = gk20a_busy(g);
-	if (err)
+	if (err) {
 		goto out_free;
+	}
 
 	nvgpu_mutex_acquire(&g->dbg_sessions_lock);
 	g->ops.gr.wait_for_pause(g, w_state);
@@ -807,8 +809,7 @@ static int nvgpu_gpu_ioctl_has_any_exception(
 static int gk20a_ctrl_get_num_vsms(struct gk20a *g,
 				    struct nvgpu_gpu_num_vsms *args)
 {
-	struct nvgpu_gr *gr = g->gr;
+	args->num_vsms = g->ops.gr.init.get_no_of_sm(g);
-	args->num_vsms = nvgpu_gr_config_get_no_of_sm(gr->config);
 	return 0;
 }
 
@@ -817,7 +818,7 @@ static int gk20a_ctrl_vsm_mapping(struct gk20a *g,
 {
 	int err = 0;
 	struct nvgpu_gr *gr = g->gr;
-	u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
+	u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
 	size_t write_size = no_of_sm *
 		sizeof(struct nvgpu_gpu_vsms_mapping_entry);
 	struct nvgpu_gpu_vsms_mapping_entry *vsms_buf;

drivers/gpu/nvgpu/os/linux/ioctl_dbg.c

@@ -45,7 +45,6 @@
 /* Access gr_gk20a_suspend_context and gr_gk20a_resume_context functions */
 #include "hal/gr/gr/gr_gk20a.h"
 
-#include "common/gr/gr_priv.h"
 #include "os_linux.h"
 #include "platform_gk20a.h"
 #include "ioctl_dbg.h"
@@ -269,7 +268,6 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
 		struct nvgpu_dbg_gpu_read_single_sm_error_state_args *args)
 {
 	struct gk20a *g = dbg_s->g;
-	struct nvgpu_gr *gr = g->gr;
 	struct nvgpu_tsg_sm_error_state *sm_error_state;
 	struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record;
 	struct channel_gk20a *ch;
@@ -289,7 +287,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
 	}
 
 	sm_id = args->sm_id;
-	if (sm_id >= nvgpu_gr_config_get_no_of_sm(gr->config)) {
+	if (sm_id >= g->ops.gr.init.get_no_of_sm(g)) {
 		return -EINVAL;
 	}
 
@@ -1454,7 +1452,6 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state(
 		struct nvgpu_dbg_gpu_clear_single_sm_error_state_args *args)
 {
 	struct gk20a *g = dbg_s->g;
-	struct nvgpu_gr *gr = g->gr;
 	u32 sm_id;
 	struct channel_gk20a *ch;
 	int err = 0;
@@ -1465,8 +1462,9 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state(
 	}
 
 	sm_id = args->sm_id;
-	if (sm_id >= nvgpu_gr_config_get_no_of_sm(gr->config))
+	if (sm_id >= g->ops.gr.init.get_no_of_sm(g)) {
 		return -EINVAL;
+	}
 
 	nvgpu_speculation_barrier();
 

drivers/gpu/nvgpu/os/linux/ioctl_tsg.c

@@ -563,15 +563,15 @@ static int gk20a_tsg_ioctl_read_single_sm_error_state(struct gk20a *g,
 		struct tsg_gk20a *tsg,
 		struct nvgpu_tsg_read_single_sm_error_state_args *args)
 {
-	struct nvgpu_gr *gr = g->gr;
 	struct nvgpu_tsg_sm_error_state *sm_error_state;
 	struct nvgpu_tsg_sm_error_state_record sm_error_state_record;
 	u32 sm_id;
 	int err = 0;
 
 	sm_id = args->sm_id;
-	if (sm_id >= nvgpu_gr_config_get_no_of_sm(gr->config))
+	if (sm_id >= g->ops.gr.init.get_no_of_sm(g)) {
 		return -EINVAL;
+	}
 
 	nvgpu_speculation_barrier();