nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Enabling/disabling FECS trace support

Browse Source 
- To enable FECS trace support, nvgpu should set the MSB
of the read pointer (MAILBOX1).
- The ucode will check if the feature is enabled/disabled
before writing a record into the circular buffer. If the
feature is disabled, it will not write the record.
- If the feature is enabled and the buffer is not allocated,
HW will throw a page fault error.

Bug 2459186

Change-Id: I8080b21d21259e863c099883d6be737e9a869e50
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109286
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vaibhav Kachore
2019-03-25 16:43:39 +05:30
committed by mobile promotions
parent 6c2c4181ae
commit c272264f54
2 changed files with 25 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/gpu/nvgpu/common/gr/fecs_trace.c
View File

@@ -272,7 +272,14 @@ int nvgpu_gr_fecs_trace_enable(struct gk20a *g)
g->ops.gr.fecs_trace.flush(g);
write = g->ops.gr.fecs_trace.get_write_index(g);
g->ops.gr.fecs_trace.set_read_index(g, write);
/*
* For enabling FECS trace support, MAILBOX1's MSB (Bit 31:31)
* should be set to 1. Bits 30:0 represents actual pointer
* value.
*/
g->ops.gr.fecs_trace.set_read_index(g, write |
(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT)));
err = nvgpu_thread_create(&trace->poll_task, g,
nvgpu_gr_fecs_trace_periodic_polling, __func__);
@@ -298,6 +305,13 @@ int nvgpu_gr_fecs_trace_disable(struct gk20a *g)
nvgpu_mutex_acquire(&trace->enable_lock);
trace->enable_count--;
if (trace->enable_count == 0U) {
/*
* For disabling FECS trace support, MAILBOX1's MSB (Bit 31:31)
* should be set to 0.
*/
g->ops.gr.fecs_trace.set_read_index(g,
g->ops.gr.fecs_trace.get_read_index(g) &
(~(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT))));
nvgpu_thread_stop(&trace->poll_task);
}
nvgpu_mutex_release(&trace->enable_lock);
@@ -483,6 +497,8 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g)
/* Ensure all FECS writes have made it to SYSMEM */
g->ops.mm.cache.fb_flush(g);
/* Bits 30:0 of MAILBOX1 represents actual read pointer value */
read = read & (~(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT)));
while (read != write) {
cnt = nvgpu_gr_fecs_trace_ring_read(g, read, &vm_update_mask);
if (cnt <= 0) {
@@ -493,6 +509,13 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g)
read = (read + 1) & (GK20A_FECS_TRACE_NUM_RECORDS - 1);
}
/*
* In the next step, read pointer is going to be updated.
* So, MSB of read pointer should be set back to 1. This will
* keep FECS trace enabled.
*/
read = read | (BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT));
/* ensure FECS records has been updated before incrementing read index */
nvgpu_wmb();
g->ops.gr.fecs_trace.set_read_index(g, read);

1
drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h
View File

@@ -55,6 +55,7 @@
((p)->tag_bits[(n) / 64] & (1 << ((n) & 63)))
#define NVGPU_GPU_CTXSW_FILTER_SIZE (NVGPU_GPU_CTXSW_TAG_LAST + 1)
#define NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT 31
struct gk20a;
struct nvgpu_mem;