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gpu: nvgpu: add hal to get the bar2 vm size

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On ga10b+ platforms, more VM space is needed to map various buffers
to bar2 vm. Engine method buffer is mapped for each pbdma and for
maximum supported TSGs this requires more than 32MB of space.
Also we need to consider fault buffer space and vab buffer
space requirement.

Bug 3958581

Change-Id: I9ee87119f762352ee12859b71c08a5f75b3554e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872811
(cherry picked from commit 53dc53a8b4)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2881179
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sagar Kamble
2023-03-17 09:22:16 +00:00
committed by mobile promotions
parent dd8f7114ba
commit 76792585b5
10 changed files with 136 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/nvgpu-hal-new.yaml
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@@ -485,7 +485,9 @@ mm:
sources: [ hal/mm/mm_gp10b_fusa.c,
hal/mm/mm_gp10b.h,
hal/mm/mm_gv11b_fusa.c,
hal/mm/mm_gv11b.h]
hal/mm/mm_gv11b.h,
hal/mm/mm_ga10b_fusa.c,
hal/mm/mm_ga10b.h]
mm:
safe: no
sources: [ hal/mm/mm_gk20a.c,

1
drivers/gpu/nvgpu/Makefile
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@@ -735,6 +735,7 @@ nvgpu-$(CONFIG_NVGPU_REMAP) += \
nvgpu-y += \
hal/mm/mm_gv11b_fusa.o \
hal/mm/mm_gp10b_fusa.o \
hal/mm/mm_ga10b_fusa.o \
hal/mm/gmmu/gmmu_gv11b_fusa.o \
hal/mm/gmmu/gmmu_gp10b_fusa.o \
hal/mm/gmmu/gmmu_gk20a_fusa.o \

1
drivers/gpu/nvgpu/Makefile.sources
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@@ -202,6 +202,7 @@ endif
# Source files below are functionaly safe (FuSa) and must always be included.
srcs += hal/mm/mm_gv11b_fusa.c \
hal/mm/mm_gp10b_fusa.c \
hal/mm/mm_ga10b_fusa.c \
hal/mm/gmmu/gmmu_gv11b_fusa.c \
hal/mm/gmmu/gmmu_gp10b_fusa.c \
hal/mm/gmmu/gmmu_gk20a_fusa.c \

4
drivers/gpu/nvgpu/hal/init/hal_ga100.c
View File

@@ -1,7 +1,7 @@
/*
* GA100 Tegra HAL interface
*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -76,6 +76,7 @@
#include "hal/mm/mm_gp10b.h"
#include "hal/mm/mm_gv11b.h"
#include "hal/mm/mm_tu104.h"
#include "hal/mm/mm_ga10b.h"
#include "hal/mm/cache/flush_gk20a.h"
#include "hal/mm/cache/flush_gv11b.h"
#include "hal/mm/gmmu/gmmu_gm20b.h"
@@ -1269,6 +1270,7 @@ static const struct gops_mm ga100_ops_mm = {
.is_bar1_supported = gv11b_mm_is_bar1_supported,
.init_inst_block = gv11b_mm_init_inst_block,
.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
.bar2_vm_size = ga10b_mm_bar2_vm_size,
.init_bar2_vm = gp10b_mm_init_bar2_vm,
.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
.get_flush_retries = tu104_mm_get_flush_retries,

4
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -1,7 +1,7 @@
/*
* GA10B Tegra HAL interface
*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,6 +53,7 @@
#include "hal/mm/mm_gp10b.h"
#include "hal/mm/mm_gv11b.h"
#include "hal/mm/mm_ga10b.h"
#include "hal/mm/cache/flush_gk20a.h"
#include "hal/mm/cache/flush_gv11b.h"
#include "hal/mm/gmmu/gmmu_gm20b.h"
@@ -1279,6 +1280,7 @@ static const struct gops_mm ga10b_ops_mm = {
.is_bar1_supported = gv11b_mm_is_bar1_supported,
.init_inst_block = gv11b_mm_init_inst_block,
.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
.bar2_vm_size = ga10b_mm_bar2_vm_size,
.init_bar2_vm = gp10b_mm_init_bar2_vm,
.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
.get_default_va_sizes = gp10b_mm_get_default_va_sizes,

30
drivers/gpu/nvgpu/hal/mm/mm_ga10b.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef HAL_MM_MM_GA10B_H
#define HAL_MM_MM_GA10B_H
struct gk20a;
u32 ga10b_mm_bar2_vm_size(struct gk20a *g);
#endif /* HAL_MM_MM_GA10B_H */

72
drivers/gpu/nvgpu/hal/mm/mm_ga10b_fusa.c Normal file
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@@ -0,0 +1,72 @@
/*
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/hw/ga10b/hw_gmmu_ga10b.h>
#include "mm_ga10b.h"
u32 ga10b_mm_bar2_vm_size(struct gk20a *g)
{
u32 num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
u32 buffer_size;
u32 fb_size;
/* Calculate engine method buffer size */
buffer_size = nvgpu_safe_add_u32(nvgpu_safe_mult_u32((9U + 1U + 3U),
g->ops.ce.get_num_pce(g)), 2U);
buffer_size = nvgpu_safe_mult_u32((27U * 5U), buffer_size);
buffer_size = PAGE_ALIGN(buffer_size);
nvgpu_log_info(g, "method buffer size in bytes %u", buffer_size);
buffer_size = nvgpu_safe_mult_u32(num_pbdma, buffer_size);
buffer_size = nvgpu_safe_mult_u32(buffer_size, g->ops.channel.count(g));
nvgpu_log_info(g, "method buffer size in bytes for max TSGs %u",
buffer_size);
/*
* Calculate fault buffers size.
* Max entries take care of 1 entry used for full detection.
*/
fb_size = nvgpu_safe_add_u32(g->ops.channel.count(g), 1U);
fb_size = nvgpu_safe_mult_u32(fb_size, gmmu_fault_buf_size_v());
/* Consider replayable and non replayable faults */
fb_size = nvgpu_safe_mult_u32(fb_size, 2U);
nvgpu_log_info(g, "fault buffers size in bytes %u", fb_size);
buffer_size = nvgpu_safe_add_u32(buffer_size, fb_size);
/* Add PAGE_SIZE for vab buffer size */
buffer_size = nvgpu_safe_add_u32(buffer_size, PAGE_SIZE);
buffer_size = PAGE_ALIGN(buffer_size);
nvgpu_log_info(g, "bar2 vm size in bytes %u", buffer_size);
return buffer_size;
}

8
drivers/gpu/nvgpu/hal/mm/mm_gp10b_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -34,8 +34,12 @@ int gp10b_mm_init_bar2_vm(struct gk20a *g)
struct nvgpu_mem *inst_block = &mm->bar2.inst_block;
u32 big_page_size = g->ops.mm.gmmu.get_default_big_page_size();
/* BAR2 aperture size is 32MB */
/* BAR2 aperture size is 32MB for chips prior to Ampere */
if (g->ops.mm.bar2_vm_size != NULL) {
mm->bar2.aperture_size = g->ops.mm.bar2_vm_size(g);
} else {
mm->bar2.aperture_size = U32(32) << 20U;
}
nvgpu_log_info(g, "bar2 vm size = 0x%x", mm->bar2.aperture_size);
mm->bar2.vm = nvgpu_vm_init(g, big_page_size, SZ_4K,

4
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
#include "hal/mm/mm_gm20b.h"
#include "hal/mm/mm_gp10b.h"
#include "hal/mm/mm_gv11b.h"
#include "hal/mm/mm_ga10b.h"
#include "hal/mm/gmmu/gmmu_gk20a.h"
#include "hal/mm/gmmu/gmmu_gm20b.h"
#include "hal/mm/gmmu/gmmu_gp10b.h"
@@ -808,6 +809,7 @@ static const struct gops_mm vgpu_ga10b_ops_mm = {
.is_bar1_supported = gv11b_mm_is_bar1_supported,
.init_inst_block = gv11b_mm_init_inst_block,
.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
.bar2_vm_size = ga10b_mm_bar2_vm_size,
.init_bar2_vm = gp10b_mm_init_bar2_vm,
.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
.vm_as_alloc_share = vgpu_vm_as_alloc_share,

14
drivers/gpu/nvgpu/include/nvgpu/gops/mm.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -512,6 +512,18 @@ struct gops_mm {
*/
bool (*is_bar1_supported)(struct gk20a *g);
/**
* @brief HAL to get the BAR2 virtual memory size in bytes.
*
* @param g [in] The GPU.
*
* - Return size needed for mapping the engine method buffers, VAB and
* fault buffers in bar2 vm.
*
* @return size in bytes.
*/
u32 (*bar2_vm_size)(struct gk20a *g);
/**
* @brief HAL to initialize the BAR2 virtual memory.
*