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gpu: nvgpu: fifo_gk20a: fix mutex_ret type

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The type used for returns from mutex functions was a u32, but should
have been an int.  This eliminates MISRA 10.3 violations by no assigning
to a different essential type.

Change-Id: Ib2356ae8c862b8b9582292edd40dfbc95d3e8fdf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930154
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2018-10-18 16:02:13 -04:00
committed by mobile promotions
parent 1b66db0c68
commit 77c3ecd75a
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -2935,7 +2935,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid)
struct fifo_gk20a *f = &g->fifo;
int ret = 0;
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
u32 mutex_ret = 0;
int mutex_ret = 0;
u32 i;
nvgpu_log_fn(g, "chid: %d", chid);
@@ -2979,7 +2979,7 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid)
struct fifo_gk20a *f = &g->fifo;
int ret = 0;
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
u32 mutex_ret = 0;
int mutex_ret = 0;
u32 i;
nvgpu_log_fn(g, "tsgid: %d", tsgid);
@@ -3050,7 +3050,7 @@ void gk20a_fifo_set_runlist_state(struct gk20a *g, u32 runlists_mask,
u32 runlist_state)
{
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
u32 mutex_ret;
int mutex_ret;
nvgpu_log(g, gpu_dbg_info, "runlist mask = 0x%08x state = 0x%08x",
runlists_mask, runlist_state);
@@ -3114,7 +3114,7 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g,
u32 pbdma_chid = FIFO_INVAL_CHANNEL_ID;
u32 engine_chid = FIFO_INVAL_CHANNEL_ID;
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
u32 mutex_ret;
int mutex_ret;
int err = 0;
nvgpu_log_fn(g, " ");
@@ -3682,7 +3682,7 @@ int nvgpu_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next,
struct gk20a *g = ch->g;
struct fifo_runlist_info_gk20a *runlist;
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
u32 mutex_ret;
int mutex_ret;
int ret = 0;
runlist = &g->fifo.runlist_info[ch->runlist_id];
@@ -3721,7 +3721,7 @@ int gk20a_fifo_update_runlist(struct gk20a *g, u32 runlist_id, u32 chid,
struct fifo_runlist_info_gk20a *runlist = NULL;
struct fifo_gk20a *f = &g->fifo;
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
u32 mutex_ret;
int mutex_ret;
int ret = 0;
nvgpu_log_fn(g, " ");