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gpu: nvgpu: Add test to cover FECS watchdog timeout

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Add unit test to cover the FECS watch timeout method
in gm20b.
Correct the file and function name to gm20b from gk20a.

Bug 200586923

Change-Id: I447e26c7d898f3967ad2de7a7e4a7457264941b5
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2290643
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2020-02-05 16:25:57 -08:00
committed by Alex Waterman
parent 86e030a18a
commit 7852d452ee
9 changed files with 54 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/libnvgpu-drv_safe.export
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@@ -82,6 +82,7 @@ gm20b_priv_ring_enum_ltc
gm20b_priv_ring_get_gpc_count gm20b_priv_ring_get_gpc_count
gm20b_priv_ring_get_fbp_count gm20b_priv_ring_get_fbp_count
gm20b_gr_falcon_submit_fecs_method_op gm20b_gr_falcon_submit_fecs_method_op
gm20b_gr_falcon_ctrl_ctxsw
gm20b_bus_bar1_bind gm20b_bus_bar1_bind
gp10b_bus_bar2_bind gp10b_bus_bar2_bind
gp10b_ce_nonstall_isr gp10b_ce_nonstall_isr

2
userspace/SWUTS.h
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@@ -143,7 +143,7 @@
* - @ref SWUTS-gr-intr * - @ref SWUTS-gr-intr
* - @ref SWUTS-gr-init-hal-gv11b * - @ref SWUTS-gr-init-hal-gv11b
* - @ref SWUTS-gr-falcon * - @ref SWUTS-gr-falcon
* - @ref SWUTS-gr-falcon-gk20a * - @ref SWUTS-gr-falcon-gm20b
* - @ref SWUTS-gr-fs-state * - @ref SWUTS-gr-fs-state
* - @ref SWUTS-gr-global-ctx * - @ref SWUTS-gr-global-ctx
* - @ref SWUTS-gr-ctx * - @ref SWUTS-gr-ctx

2
userspace/SWUTS.sources
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@@ -115,7 +115,7 @@ INPUT += ../../../userspace/units/gr/setup/nvgpu-gr-setup.h
INPUT += ../../../userspace/units/gr/intr/nvgpu-gr-intr.h INPUT += ../../../userspace/units/gr/intr/nvgpu-gr-intr.h
INPUT += ../../../userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.h INPUT += ../../../userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.h
INPUT += ../../../userspace/units/gr/falcon/nvgpu-gr-falcon.h INPUT += ../../../userspace/units/gr/falcon/nvgpu-gr-falcon.h
INPUT += ../../../userspace/units/gr/falcon/nvgpu-gr-falcon-gk20a.h INPUT += ../../../userspace/units/gr/falcon/nvgpu-gr-falcon-gm20b.h
INPUT += ../../../userspace/units/gr/fs_state/nvgpu-gr-fs-state.h INPUT += ../../../userspace/units/gr/fs_state/nvgpu-gr-fs-state.h
INPUT += ../../../userspace/units/gr/global_ctx/nvgpu-gr-global-ctx.h INPUT += ../../../userspace/units/gr/global_ctx/nvgpu-gr-global-ctx.h
INPUT += ../../../userspace/units/gr/ctx/nvgpu-gr-ctx.h INPUT += ../../../userspace/units/gr/ctx/nvgpu-gr-ctx.h

4
userspace/required_tests.json
View File

@@ -2700,8 +2700,8 @@
"test_level": 0 "test_level": 0
}, },
{ {
"test": "test_gr_falcon_gk20a_ctrl_ctxsw", "test": "test_gr_falcon_gm20b_ctrl_ctxsw",
"case": "gr_falcon_gk20a_ctrl_ctxsw", "case": "gr_falcon_gm20b_ctrl_ctxsw",
"unit": "nvgpu_gr_falcon", "unit": "nvgpu_gr_falcon",
"test_level": 0 "test_level": 0
}, },

4
userspace/units/gr/falcon/Makefile
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. # Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
# #
# Permission is hereby granted, free of charge, to any person obtaining a # Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"), # copy of this software and associated documentation files (the "Software"),
@@ -21,7 +21,7 @@
.SUFFIXES: .SUFFIXES:
OBJS = nvgpu-gr-falcon.o \ OBJS = nvgpu-gr-falcon.o \
nvgpu-gr-falcon-gk20a.o nvgpu-gr-falcon-gm20b.o
MODULE = nvgpu-gr-falcon MODULE = nvgpu-gr-falcon

4
userspace/units/gr/falcon/Makefile.tmk
View File

@@ -1,6 +1,6 @@
################################### tell Emacs this is a -*- makefile-gmake -*- ################################### tell Emacs this is a -*- makefile-gmake -*-
# #
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. # Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
# #
# Permission is hereby granted, free of charge, to any person obtaining a # Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"), # copy of this software and associated documentation files (the "Software"),
@@ -26,7 +26,7 @@
NVGPU_UNIT_NAME = nvgpu-gr-falcon NVGPU_UNIT_NAME = nvgpu-gr-falcon
NVGPU_UNIT_SRCS = nvgpu-gr-falcon.c \ NVGPU_UNIT_SRCS = nvgpu-gr-falcon.c \
nvgpu-gr-falcon-gk20a.c nvgpu-gr-falcon-gm20b.c
NVGPU_UNIT_INTERFACE_DIRS := \ NVGPU_UNIT_INTERFACE_DIRS := \
$(NV_COMPONENT_DIR)/.. \ $(NV_COMPONENT_DIR)/.. \

45
userspace/units/gr/falcon/nvgpu-gr-falcon-gk20a.c → userspace/units/gr/falcon/nvgpu-gr-falcon-gm20b.c
View File

@@ -43,9 +43,9 @@
#include "hal/gr/falcon/gr_falcon_gm20b.h" #include "hal/gr/falcon/gr_falcon_gm20b.h"
#include "../nvgpu-gr.h" #include "../nvgpu-gr.h"
#include "nvgpu-gr-falcon-gk20a.h" #include "nvgpu-gr-falcon-gm20b.h"
struct gr_falcon_gk20a_fecs_op { struct gr_falcon_gm20b_fecs_op {
u32 id; u32 id;
u32 data; u32 data;
u32 ok; u32 ok;
@@ -60,7 +60,13 @@ static void gr_falcon_fecs_dump_stats(struct gk20a *g)
/* Do Nothing */ /* Do Nothing */
} }
static int gr_falcon_gk20a_submit_fecs_mthd_op(struct unit_module *m, static int gr_falcon_ctrl_ctxsw_stub(struct gk20a *g, u32 fecs_method,
u32 data, u32 *ret_val)
{
return -EINVAL;
}
static int gr_falcon_gm20b_submit_fecs_mthd_op(struct unit_module *m,
struct gk20a *g) struct gk20a *g)
{ {
int err, i; int err, i;
@@ -72,7 +78,7 @@ static int gr_falcon_gk20a_submit_fecs_mthd_op(struct unit_module *m,
.cond.fail = GR_IS_UCODE_OP_SKIP, .cond.fail = GR_IS_UCODE_OP_SKIP,
}; };
struct gr_falcon_gk20a_fecs_op fecs_op_stat[] = { struct gr_falcon_gm20b_fecs_op fecs_op_stat[] = {
[0] = { [0] = {
.id = 4U, .id = 4U,
.data = 0U, .data = 0U,
@@ -147,7 +153,7 @@ static int gr_falcon_gk20a_submit_fecs_mthd_op(struct unit_module *m,
}, },
}; };
int arry_cnt = sizeof(fecs_op_stat)/ int arry_cnt = sizeof(fecs_op_stat)/
sizeof(struct gr_falcon_gk20a_fecs_op); sizeof(struct gr_falcon_gm20b_fecs_op);
g->ops.gr.falcon.dump_stats = gr_falcon_fecs_dump_stats; g->ops.gr.falcon.dump_stats = gr_falcon_fecs_dump_stats;
for (i = 0; i < arry_cnt; i++) { for (i = 0; i < arry_cnt; i++) {
@@ -177,6 +183,9 @@ static int gr_falcon_timer_init_error(struct unit_module *m,
struct nvgpu_gr_falcon_query_sizes sizes; struct nvgpu_gr_falcon_query_sizes sizes;
struct nvgpu_posix_fault_inj *timer_fi = struct nvgpu_posix_fault_inj *timer_fi =
nvgpu_timers_get_fault_injection(); nvgpu_timers_get_fault_injection();
int (*gr_falcon_ctrl_ctxsw_local)(struct gk20a *g,
u32 fecs_method,
u32 data, u32 *ret_val);
nvgpu_posix_enable_fault_injection(timer_fi, true, 0); nvgpu_posix_enable_fault_injection(timer_fi, true, 0);
err = g->ops.gr.falcon.wait_mem_scrubbing(g); err = g->ops.gr.falcon.wait_mem_scrubbing(g);
@@ -233,6 +242,15 @@ static int gr_falcon_timer_init_error(struct unit_module *m,
} }
nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
gr_falcon_ctrl_ctxsw_local = g->ops.gr.falcon.ctrl_ctxsw;
g->ops.gr.falcon.ctrl_ctxsw = gr_falcon_ctrl_ctxsw_stub;
err = g->ops.gr.falcon.wait_ctxsw_ready(g);
if (err == 0) {
unit_return_fail(m,
"gr_falcon_wait_ctxsw_ready failed\n");
}
g->ops.gr.falcon.ctrl_ctxsw = gr_falcon_ctrl_ctxsw_local;
err = g->ops.gr.falcon.wait_ctxsw_ready(g); err = g->ops.gr.falcon.wait_ctxsw_ready(g);
if (err != 0) { if (err != 0) {
unit_return_fail(m, unit_return_fail(m,
@@ -242,22 +260,29 @@ static int gr_falcon_timer_init_error(struct unit_module *m,
return UNIT_SUCCESS; return UNIT_SUCCESS;
} }
int test_gr_falcon_gk20a_ctrl_ctxsw(struct unit_module *m, int test_gr_falcon_gm20b_ctrl_ctxsw(struct unit_module *m,
struct gk20a *g, void *args) struct gk20a *g, void *args)
{ {
int err = 0; int err = 0;
u32 data = 0; u32 data = 0;
err = gm20b_gr_falcon_ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_SET_WATCHDOG_TIMEOUT, data, NULL);
if (err) {
unit_return_fail(m,
"falcon_gm20b_ctrl_ctxsw watchdog timeout failed\n");
}
err = g->ops.gr.falcon.ctrl_ctxsw(g, err = g->ops.gr.falcon.ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_GOLDEN_IMAGE_SAVE, data, NULL); NVGPU_GR_FALCON_METHOD_GOLDEN_IMAGE_SAVE, data, NULL);
if (err) { if (err) {
unit_return_fail(m, "falcon_gk20a_ctrl_ctxsw failed\n"); unit_return_fail(m, "falcon_gm20b_ctrl_ctxsw failed\n");
} }
/* Invalid Method */ /* Invalid Method */
err = g->ops.gr.falcon.ctrl_ctxsw(g, 0, data, NULL); err = g->ops.gr.falcon.ctrl_ctxsw(g, 0, data, NULL);
if (err) { if (err) {
unit_return_fail(m, "falcon_gk20a_ctrl_ctxsw failed\n"); unit_return_fail(m, "falcon_gm20b_ctrl_ctxsw failed\n");
} }
err = gr_falcon_timer_init_error(m, g); err = gr_falcon_timer_init_error(m, g);
@@ -265,9 +290,9 @@ int test_gr_falcon_gk20a_ctrl_ctxsw(struct unit_module *m,
unit_return_fail(m, "gr_falcon_timer_init_error failed\n"); unit_return_fail(m, "gr_falcon_timer_init_error failed\n");
} }
err = gr_falcon_gk20a_submit_fecs_mthd_op(m, g); err = gr_falcon_gm20b_submit_fecs_mthd_op(m, g);
if (err) { if (err) {
unit_return_fail(m, "gr_falcon_gk20a_fecs_mthd_op failed\n"); unit_return_fail(m, "gr_falcon_gm20b_fecs_mthd_op failed\n");
} }
return UNIT_SUCCESS; return UNIT_SUCCESS;

13
userspace/units/gr/falcon/nvgpu-gr-falcon-gk20a.h → userspace/units/gr/falcon/nvgpu-gr-falcon-gm20b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -19,22 +19,22 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#ifndef UNIT_NVGPU_GR_FALCON_GK20A_H #ifndef UNIT_NVGPU_GR_FALCON_GM20B_H
#define UNIT_NVGPU_GR_FALCON_GK20A_H #define UNIT_NVGPU_GR_FALCON_GM20B_H
#include <nvgpu/types.h> #include <nvgpu/types.h>
struct unit_module; struct unit_module;
struct gk20a; struct gk20a;
/** @addtogroup SWUTS-gr-falcon-gk20a /** @addtogroup SWUTS-gr-falcon-gm20b
* @{ * @{
* *
* Software Unit Test Specification for common.gr.falcon * Software Unit Test Specification for common.gr.falcon
*/ */
/** /**
* Test specification for: test_gr_falcon_gk20a_ctrl_ctxsw * Test specification for: test_gr_falcon_gm20b_ctrl_ctxsw
* *
* Description: Helps to verify various failure and conditional checking * Description: Helps to verify various failure and conditional checking
* in falcon gm20b hal functions. * in falcon gm20b hal functions.
@@ -51,6 +51,7 @@ struct gk20a;
* gm20b_gr_falcon_ctrl_ctxsw * gm20b_gr_falcon_ctrl_ctxsw
* *
* Steps: * Steps:
* - Call gm20b_gr_falcon_ctrl_ctxsw with watchdog timeout Method.
* - Call g->ops.gr.falcon.ctrl_ctxsw with Invalid Method. * - Call g->ops.gr.falcon.ctrl_ctxsw with Invalid Method.
* - Enable timer init failure injection in various functions. * - Enable timer init failure injection in various functions.
* - g->ops.gr.falcon.wait_ctxsw_ready. * - g->ops.gr.falcon.wait_ctxsw_ready.
@@ -62,7 +63,7 @@ struct gk20a;
* *
* Output: Returns PASS if all branches gave expected results. FAIL otherwise. * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/ */
int test_gr_falcon_gk20a_ctrl_ctxsw(struct unit_module *m, int test_gr_falcon_gm20b_ctrl_ctxsw(struct unit_module *m,
struct gk20a *g, void *args); struct gk20a *g, void *args);
/** /**
* @} * @}

6
userspace/units/gr/falcon/nvgpu-gr-falcon.c
View File

@@ -46,7 +46,7 @@
#include "hal/gr/falcon/gr_falcon_gm20b.h" #include "hal/gr/falcon/gr_falcon_gm20b.h"
#include "../nvgpu-gr.h" #include "../nvgpu-gr.h"
#include "nvgpu-gr-falcon-gk20a.h" #include "nvgpu-gr-falcon-gm20b.h"
#include "nvgpu-gr-falcon.h" #include "nvgpu-gr-falcon.h"
struct gr_gops_falcon_orgs { struct gr_gops_falcon_orgs {
@@ -372,8 +372,8 @@ struct unit_module_test nvgpu_gr_falcon_tests[] = {
test_gr_falcon_init_ctx_state, NULL, 0), test_gr_falcon_init_ctx_state, NULL, 0),
UNIT_TEST(gr_falcon_fail_ctxsw_ucode, UNIT_TEST(gr_falcon_fail_ctxsw_ucode,
test_gr_falcon_fail_ctxsw_ucode, NULL, 0), test_gr_falcon_fail_ctxsw_ucode, NULL, 0),
UNIT_TEST(gr_falcon_gk20a_ctrl_ctxsw, UNIT_TEST(gr_falcon_gm20b_ctrl_ctxsw,
test_gr_falcon_gk20a_ctrl_ctxsw, NULL, 0), test_gr_falcon_gm20b_ctrl_ctxsw, NULL, 0),
UNIT_TEST(gr_falcon_deinit, test_gr_falcon_deinit, NULL, 0), UNIT_TEST(gr_falcon_deinit, test_gr_falcon_deinit, NULL, 0),
}; };