Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel

Merge T186 - gp10b/gp106 code into common nvgpu repo

Bug 200266498

Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>

drivers/gpu/nvgpu/Makefile.nvgpu-t18x

@@ -0,0 +1,75 @@
+nvgpu-t18x := $(call tegra-path,nvgpu-t18x,drivers/gpu/nvgpu)
+
+nvgpu-y += \
+	$(nvgpu-t18x)/gp10b/gr_gp10b.o  \
+	$(nvgpu-t18x)/gp10b/gr_ctx_gp10b.o  \
+	$(nvgpu-t18x)/gp10b/ce_gp10b.o \
+	$(nvgpu-t18x)/gp10b/mc_gp10b.o  \
+	$(nvgpu-t18x)/gp10b/fifo_gp10b.o  \
+	$(nvgpu-t18x)/gp10b/ltc_gp10b.o \
+	$(nvgpu-t18x)/gp10b/mm_gp10b.o \
+	$(nvgpu-t18x)/gp10b/fb_gp10b.o \
+	$(nvgpu-t18x)/gp10b/pmu_gp10b.o \
+	$(nvgpu-t18x)/gp10b/hal_gp10b.o \
+	$(nvgpu-t18x)/gp10b/rpfb_gp10b.o \
+	$(nvgpu-t18x)/gp10b/gp10b_gating_reglist.o \
+	$(nvgpu-t18x)/gp10b/regops_gp10b.o \
+	$(nvgpu-t18x)/gp10b/cde_gp10b.o \
+	$(nvgpu-t18x)/gp10b/therm_gp10b.o \
+	$(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \
+	$(nvgpu-t18x)/gp10b/gp10b_sysfs.o \
+	$(nvgpu-t18x)/gp10b/gp10b.o \
+	$(nvgpu-t18x)/gp106/hal_gp106.o \
+	$(nvgpu-t18x)/gp106/mm_gp106.o \
+	$(nvgpu-t18x)/gp106/pmu_gp106.o \
+	$(nvgpu-t18x)/gp106/gr_gp106.o \
+	$(nvgpu-t18x)/gp106/gr_ctx_gp106.o \
+	$(nvgpu-t18x)/gp106/acr_gp106.o \
+	$(nvgpu-t18x)/gp106/sec2_gp106.o \
+	$(nvgpu-t18x)/gp106/fifo_gp106.o \
+	$(nvgpu-t18x)/gp106/ltc_gp106.o \
+	$(nvgpu-t18x)/gp106/fb_gp106.o \
+	$(nvgpu-t18x)/gp106/bios_gp106.o \
+	$(nvgpu-t18x)/gp106/regops_gp106.o \
+	$(nvgpu-t18x)/clk/clk_mclk.o \
+	$(nvgpu-t18x)/pstate/pstate.o \
+	$(nvgpu-t18x)/clk/clk_vin.o \
+	$(nvgpu-t18x)/clk/clk_fll.o \
+	$(nvgpu-t18x)/clk/clk_domain.o \
+	$(nvgpu-t18x)/clk/clk_prog.o \
+	$(nvgpu-t18x)/clk/clk_vf_point.o \
+	$(nvgpu-t18x)/clk/clk_arb.o \
+	$(nvgpu-t18x)/clk/clk_freq_controller.o \
+	$(nvgpu-t18x)/perf/vfe_var.o \
+	$(nvgpu-t18x)/perf/vfe_equ.o \
+	$(nvgpu-t18x)/perf/perf.o \
+	$(nvgpu-t18x)/clk/clk.o \
+	$(nvgpu-t18x)/gp106/clk_gp106.o \
+	$(nvgpu-t18x)/gp106/clk_arb_gp106.o \
+	$(nvgpu-t18x)/gp106/gp106_gating_reglist.o \
+	$(nvgpu-t18x)/gp106/xve_gp106.o \
+	$(nvgpu-t18x)/gp106/therm_gp106.o \
+	$(nvgpu-t18x)/gp106/xve_gp106.o \
+	$(nvgpu-t18x)/pmgr/pwrdev.o \
+	$(nvgpu-t18x)/pmgr/pmgr.o \
+	$(nvgpu-t18x)/pmgr/pmgrpmu.o \
+	$(nvgpu-t18x)/pmgr/pwrmonitor.o \
+	$(nvgpu-t18x)/pmgr/pwrpolicy.o \
+	$(nvgpu-t18x)/volt/volt_rail.o \
+	$(nvgpu-t18x)/volt/volt_dev.o \
+	$(nvgpu-t18x)/volt/volt_policy.o \
+	$(nvgpu-t18x)/volt/volt_pmu.o \
+	$(nvgpu-t18x)/therm/thrm.o \
+	$(nvgpu-t18x)/therm/thrmdev.o \
+	$(nvgpu-t18x)/therm/thrmchannel.o \
+	$(nvgpu-t18x)/therm/thrmpmu.o \
+	$(nvgpu-t18x)/lpwr/rppg.o \
+	$(nvgpu-t18x)/lpwr/lpwr.o
+
+nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o
+
+nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
+	$(nvgpu-t18x)/vgpu/gp10b/vgpu_hal_gp10b.o  \
+	$(nvgpu-t18x)/vgpu/gp10b/vgpu_gr_gp10b.o  \
+	$(nvgpu-t18x)/vgpu/gp10b/vgpu_mm_gp10b.o \
+	$(nvgpu-t18x)/vgpu/gp10b/vgpu_fifo_gp10b.o

drivers/gpu/nvgpu/acr_t18x.h

@@ -0,0 +1,20 @@
+/*
+ * NVIDIA T18x ACR
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#ifndef _NVGPU_ACR_T18X_H_
+#define _NVGPU_ACR_T18X_H_
+
+#include "gp106/acr_gp106.h"
+
+#endif

drivers/gpu/nvgpu/clk/clk.c

@@ -0,0 +1,529 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "clk.h"
+#include "pmuif/gpmuifclk.h"
+#include "pmuif/gpmuifvolt.h"
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlvolt.h"
+#include "volt/volt.h"
+#include "gk20a/pmu_gk20a.h"
+
+#define BOOT_GPC2CLK_MHZ  2581
+#define BOOT_MCLK_MHZ     3003
+
+struct clkrpc_pmucmdhandler_params {
+	struct nv_pmu_clk_rpc *prpccall;
+	u32 success;
+};
+
+static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
+				 void *param, u32 handle, u32 status)
+{
+	struct clkrpc_pmucmdhandler_params *phandlerparams =
+		(struct clkrpc_pmucmdhandler_params *)param;
+
+	gk20a_dbg_info("");
+
+	if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) {
+		gk20a_err(dev_from_gk20a(g),
+			  "unsupported msg for VFE LOAD RPC %x",
+			  msg->msg.clk.msg_type);
+		return;
+	}
+
+	if (phandlerparams->prpccall->b_supported)
+		phandlerparams->success = 1;
+}
+
+int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
+{
+	struct pmu_cmd cmd;
+	struct pmu_msg msg;
+	struct pmu_payload payload = { {0} };
+	u32 status;
+	u32 seqdesc;
+	struct nv_pmu_clk_rpc rpccall = {0};
+	struct clkrpc_pmucmdhandler_params handler = {0};
+	struct nv_pmu_clk_load *clkload;
+	struct clk_freq_controllers *pclk_freq_controllers;
+	struct ctrl_boardobjgrp_mask_e32 *load_mask;
+
+	pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
+	rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
+	clkload = &rpccall.params.clk_load;
+	clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER;
+	clkload->action_mask = bload ?
+		NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES :
+		NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO;
+
+	load_mask = &rpccall.params.clk_load.payload.freq_controllers.load_mask;
+
+	status = boardobjgrpmask_export(
+		&pclk_freq_controllers->freq_ctrl_load_mask.super,
+		pclk_freq_controllers->freq_ctrl_load_mask.super.bitcount,
+		&load_mask->super);
+
+	cmd.hdr.unit_id = PMU_UNIT_CLK;
+	cmd.hdr.size =  (u32)sizeof(struct nv_pmu_clk_cmd) +
+			(u32)sizeof(struct pmu_hdr);
+
+	cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
+	msg.hdr.size = sizeof(struct pmu_msg);
+
+	payload.in.buf = (u8 *)&rpccall;
+	payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
+	payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
+	payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;
+
+	payload.out.buf = (u8 *)&rpccall;
+	payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
+	payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
+	payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
+
+	handler.prpccall = &rpccall;
+	handler.success = 0;
+	status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
+			PMU_COMMAND_QUEUE_LPQ,
+			clkrpc_pmucmdhandler, (void *)&handler,
+			&seqdesc, ~0);
+
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"unable to post clk RPC cmd %x",
+			cmd.cmd.clk.cmd_type);
+		goto done;
+	}
+
+	pmu_wait_message_cond(&g->pmu,
+			gk20a_get_gr_idle_timeout(g),
+			&handler.success, 1);
+
+	if (handler.success == 0) {
+		gk20a_err(dev_from_gk20a(g), "rpc call to load freq cntlr cal failed");
+		status = -EINVAL;
+	}
+
+done:
+	return status;
+}
+
+u32 clk_pmu_vin_load(struct gk20a *g)
+{
+	struct pmu_cmd cmd;
+	struct pmu_msg msg;
+	struct pmu_payload payload = { {0} };
+	u32 status;
+	u32 seqdesc;
+	struct nv_pmu_clk_rpc rpccall = {0};
+	struct clkrpc_pmucmdhandler_params handler = {0};
+	struct nv_pmu_clk_load *clkload;
+
+	rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
+	clkload = &rpccall.params.clk_load;
+	clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN;
+	clkload->action_mask = NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES << 4;
+
+	cmd.hdr.unit_id = PMU_UNIT_CLK;
+	cmd.hdr.size =  (u32)sizeof(struct nv_pmu_clk_cmd) +
+			(u32)sizeof(struct pmu_hdr);
+
+	cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
+	msg.hdr.size = sizeof(struct pmu_msg);
+
+	payload.in.buf = (u8 *)&rpccall;
+	payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
+	payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
+	payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;
+
+	payload.out.buf = (u8 *)&rpccall;
+	payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
+	payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
+	payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
+
+	handler.prpccall = &rpccall;
+	handler.success = 0;
+	status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
+			PMU_COMMAND_QUEUE_LPQ,
+			clkrpc_pmucmdhandler, (void *)&handler,
+			&seqdesc, ~0);
+
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"unable to post clk RPC cmd %x",
+			cmd.cmd.clk.cmd_type);
+		goto done;
+	}
+
+	pmu_wait_message_cond(&g->pmu,
+			gk20a_get_gr_idle_timeout(g),
+			&handler.success, 1);
+
+	if (handler.success == 0) {
+		gk20a_err(dev_from_gk20a(g), "rpc call to load vin cal failed");
+		status = -EINVAL;
+	}
+
+done:
+	return status;
+}
+
+static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
+{
+	struct pmu_cmd cmd;
+	struct pmu_msg msg;
+	struct pmu_payload payload = { {0} };
+	u32 status;
+	u32 seqdesc;
+	struct nv_pmu_clk_rpc rpccall = {0};
+	struct clkrpc_pmucmdhandler_params handler = {0};
+	struct nv_pmu_clk_vf_change_inject *vfchange;
+
+	if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) ||
+		(setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0))
+		return -EINVAL;
+
+	if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) ||
+		(setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) ||
+		(setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR))
+		return -EINVAL;
+
+	rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT;
+	vfchange = &rpccall.params.clk_vf_change_inject;
+	vfchange->flags = 0;
+	vfchange->clk_list.num_domains = 3;
+	vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPC2CLK;
+	vfchange->clk_list.clk_domains[0].clk_freq_khz =
+					setfllclk->gpc2clkmhz * 1000;
+	vfchange->clk_list.clk_domains[0].clk_flags = 0;
+	vfchange->clk_list.clk_domains[0].current_regime_id =
+		setfllclk->current_regime_id_gpc;
+	vfchange->clk_list.clk_domains[0].target_regime_id =
+		setfllclk->target_regime_id_gpc;
+	vfchange->clk_list.clk_domains[1].clk_domain = CTRL_CLK_DOMAIN_XBAR2CLK;
+	vfchange->clk_list.clk_domains[1].clk_freq_khz =
+					setfllclk->xbar2clkmhz * 1000;
+	vfchange->clk_list.clk_domains[1].clk_flags = 0;
+	vfchange->clk_list.clk_domains[1].current_regime_id =
+		setfllclk->current_regime_id_xbar;
+	vfchange->clk_list.clk_domains[1].target_regime_id =
+		setfllclk->target_regime_id_xbar;
+	vfchange->clk_list.clk_domains[2].clk_domain = CTRL_CLK_DOMAIN_SYS2CLK;
+	vfchange->clk_list.clk_domains[2].clk_freq_khz =
+					setfllclk->sys2clkmhz * 1000;
+	vfchange->clk_list.clk_domains[2].clk_flags = 0;
+	vfchange->clk_list.clk_domains[2].current_regime_id =
+		setfllclk->current_regime_id_sys;
+	vfchange->clk_list.clk_domains[2].target_regime_id =
+		setfllclk->target_regime_id_sys;
+	vfchange->volt_list.num_rails = 1;
+	vfchange->volt_list.rails[0].volt_domain = CTRL_VOLT_DOMAIN_LOGIC;
+	vfchange->volt_list.rails[0].voltage_uv = setfllclk->voltuv;
+	vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv =
+				setfllclk->voltuv;
+
+	cmd.hdr.unit_id = PMU_UNIT_CLK;
+	cmd.hdr.size =  (u32)sizeof(struct nv_pmu_clk_cmd) +
+			(u32)sizeof(struct pmu_hdr);
+
+	cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
+	msg.hdr.size = sizeof(struct pmu_msg);
+
+	payload.in.buf = (u8 *)&rpccall;
+	payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
+	payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
+	payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;
+
+	payload.out.buf = (u8 *)&rpccall;
+	payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
+	payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
+	payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
+
+	handler.prpccall = &rpccall;
+	handler.success = 0;
+
+	status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
+			PMU_COMMAND_QUEUE_LPQ,
+			clkrpc_pmucmdhandler, (void *)&handler,
+			&seqdesc, ~0);
+
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			  "unable to post clk RPC cmd %x",
+			  cmd.cmd.clk.cmd_type);
+		goto done;
+	}
+
+	pmu_wait_message_cond(&g->pmu,
+			gk20a_get_gr_idle_timeout(g),
+			&handler.success, 1);
+
+	if (handler.success == 0) {
+		gk20a_err(dev_from_gk20a(g), "rpc call to inject clock failed");
+		status = -EINVAL;
+	}
+done:
+	return status;
+}
+
+static u32 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz)
+{
+	struct fll_device *pflldev;
+	u8 j;
+	struct clk_pmupstate *pclk = &g->clk_pmu;
+
+	BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
+		struct fll_device *, pflldev, j) {
+		if (pflldev->clk_domain == domain) {
+			if (pflldev->regime_desc.fixed_freq_regime_limit_mhz >=
+							clkmhz)
+				return CTRL_CLK_FLL_REGIME_ID_FFR;
+			else
+				return CTRL_CLK_FLL_REGIME_ID_FR;
+		}
+	}
+	return CTRL_CLK_FLL_REGIME_ID_INVALID;
+}
+
+static int set_regime_id(struct gk20a *g, u32 domain, u32 regimeid)
+{
+	struct fll_device *pflldev;
+	u8 j;
+	struct clk_pmupstate *pclk = &g->clk_pmu;
+
+	BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
+		struct fll_device *, pflldev, j) {
+		if (pflldev->clk_domain == domain) {
+			pflldev->regime_desc.regime_id = regimeid;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static int get_regime_id(struct gk20a *g, u32 domain, u32 *regimeid)
+{
+	struct fll_device *pflldev;
+	u8 j;
+	struct clk_pmupstate *pclk = &g->clk_pmu;
+
+	BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
+		struct fll_device *, pflldev, j) {
+		if (pflldev->clk_domain == domain) {
+			*regimeid = pflldev->regime_desc.regime_id;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk)
+{
+	int status = -EINVAL;
+
+	/*set regime ids */
+	status = get_regime_id(g, CTRL_CLK_DOMAIN_GPC2CLK,
+			&setfllclk->current_regime_id_gpc);
+	if (status)
+		goto done;
+
+	setfllclk->target_regime_id_gpc = find_regime_id(g,
+			CTRL_CLK_DOMAIN_GPC2CLK, setfllclk->gpc2clkmhz);
+
+	status = get_regime_id(g, CTRL_CLK_DOMAIN_SYS2CLK,
+			&setfllclk->current_regime_id_sys);
+	if (status)
+		goto done;
+
+	setfllclk->target_regime_id_sys = find_regime_id(g,
+			CTRL_CLK_DOMAIN_SYS2CLK, setfllclk->sys2clkmhz);
+
+	status = get_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK,
+			&setfllclk->current_regime_id_xbar);
+	if (status)
+		goto done;
+
+	setfllclk->target_regime_id_xbar = find_regime_id(g,
+			CTRL_CLK_DOMAIN_XBAR2CLK, setfllclk->xbar2clkmhz);
+
+	status = clk_pmu_vf_inject(g, setfllclk);
+
+	if (status)
+		gk20a_err(dev_from_gk20a(g),
+			"vf inject to change clk failed");
+
+	/* save regime ids */
+	status = set_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK,
+			setfllclk->target_regime_id_xbar);
+	if (status)
+		goto done;
+
+	status = set_regime_id(g, CTRL_CLK_DOMAIN_GPC2CLK,
+			setfllclk->target_regime_id_gpc);
+	if (status)
+		goto done;
+
+	status = set_regime_id(g, CTRL_CLK_DOMAIN_SYS2CLK,
+			setfllclk->target_regime_id_sys);
+	if (status)
+		goto done;
+done:
+	return status;
+}
+
+int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk)
+{
+	int status = -EINVAL;
+	struct clk_domain *pdomain;
+	u8 i;
+	struct clk_pmupstate *pclk = &g->clk_pmu;
+	u16 clkmhz = 0;
+	struct clk_domain_3x_master *p3xmaster;
+	struct clk_domain_3x_slave *p3xslave;
+	unsigned long slaveidxmask;
+
+	if (setfllclk->gpc2clkmhz == 0)
+		return -EINVAL;
+
+	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
+			struct clk_domain *, pdomain, i) {
+
+		if (pdomain->api_domain == CTRL_CLK_DOMAIN_GPC2CLK) {
+
+			if (!pdomain->super.implements(g, &pdomain->super,
+				CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER)) {
+				status = -EINVAL;
+				goto done;
+			}
+			p3xmaster = (struct clk_domain_3x_master *)pdomain;
+			slaveidxmask = p3xmaster->slave_idxs_mask;
+			for_each_set_bit(i, &slaveidxmask, 32) {
+				p3xslave = (struct clk_domain_3x_slave *)
+						CLK_CLK_DOMAIN_GET(pclk, i);
+				if ((p3xslave->super.super.super.api_domain !=
+				     CTRL_CLK_DOMAIN_XBAR2CLK) &&
+				    (p3xslave->super.super.super.api_domain !=
+				     CTRL_CLK_DOMAIN_SYS2CLK))
+					continue;
+				clkmhz = 0;
+				status = p3xslave->clkdomainclkgetslaveclk(g,
+						pclk,
+						(struct clk_domain *)p3xslave,
+						&clkmhz,
+						setfllclk->gpc2clkmhz);
+				if (status) {
+					status = -EINVAL;
+					goto done;
+				}
+				if (p3xslave->super.super.super.api_domain ==
+				     CTRL_CLK_DOMAIN_XBAR2CLK)
+					setfllclk->xbar2clkmhz = clkmhz;
+				if (p3xslave->super.super.super.api_domain ==
+				     CTRL_CLK_DOMAIN_SYS2CLK)
+					setfllclk->sys2clkmhz = clkmhz;
+			}
+		}
+	}
+done:
+	return status;
+}
+
+u32 clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain)
+{
+	u32 status = -EINVAL;
+	struct clk_domain *pdomain;
+	u8 i;
+	struct clk_pmupstate *pclk = &g->clk_pmu;
+	u16 clkmhz = 0;
+	u32 volt = 0;
+
+	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
+			struct clk_domain *, pdomain, i) {
+		if (pdomain->api_domain == clkapidomain) {
+			status = pdomain->clkdomainclkvfsearch(g, pclk,
+				pdomain, &clkmhz, &volt,
+				CLK_PROG_VFE_ENTRY_LOGIC);
+			status = pdomain->clkdomainclkvfsearch(g, pclk,
+				pdomain, &clkmhz, &volt,
+				CLK_PROG_VFE_ENTRY_SRAM);
+		}
+	}
+	return status;
+}
+
+u32 clk_domain_get_f_or_v(
+	struct gk20a *g,
+	u32 clkapidomain,
+	u16 *pclkmhz,
+	u32 *pvoltuv,
+	u8 railidx
+)
+{
+	u32 status = -EINVAL;
+	struct clk_domain *pdomain;
+	u8 i;
+	struct clk_pmupstate *pclk = &g->clk_pmu;
+	u8 rail;
+
+	if ((pclkmhz == NULL) || (pvoltuv == NULL))
+		return -EINVAL;
+
+	if (railidx == CTRL_VOLT_DOMAIN_LOGIC)
+		rail = CLK_PROG_VFE_ENTRY_LOGIC;
+	else if (railidx == CTRL_VOLT_DOMAIN_SRAM)
+		rail = CLK_PROG_VFE_ENTRY_SRAM;
+	else
+		return -EINVAL;
+
+	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
+			struct clk_domain *, pdomain, i) {
+		if (pdomain->api_domain == clkapidomain) {
+			status = pdomain->clkdomainclkvfsearch(g, pclk,
+				pdomain, pclkmhz, pvoltuv, rail);
+			return status;
+		}
+	}
+	return status;
+}
+
+u32 clk_domain_get_f_points(
+	struct gk20a *g,
+	u32 clkapidomain,
+	u32 *pfpointscount,
+	u16 *pfreqpointsinmhz
+)
+{
+	u32 status = -EINVAL;
+	struct clk_domain *pdomain;
+	u8 i;
+	struct clk_pmupstate *pclk = &g->clk_pmu;
+
+	if (pfpointscount == NULL)
+		return -EINVAL;
+
+	if ((pfreqpointsinmhz == NULL) && (*pfpointscount != 0))
+		return -EINVAL;
+
+	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
+			struct clk_domain *, pdomain, i) {
+		if (pdomain->api_domain == clkapidomain) {
+			status = pdomain->clkdomainclkgetfpoints(g, pclk,
+				pdomain, pfpointscount,
+				pfreqpointsinmhz,
+				CLK_PROG_VFE_ENTRY_LOGIC);
+			return status;
+		}
+	}
+	return status;
+}

drivers/gpu/nvgpu/clk/clk.h

@@ -0,0 +1,120 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#ifndef _CLK_H_
+#define _CLK_H_
+
+#include "clk_vin.h"
+#include "clk_fll.h"
+#include "clk_domain.h"
+#include "clk_prog.h"
+#include "clk_vf_point.h"
+#include "clk_mclk.h"
+#include "clk_freq_controller.h"
+#include "gk20a/gk20a.h"
+
+#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10
+#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK 0x1F
+#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SHIFT 0
+
+/* clock related defines for GPUs supporting clock control from pmu*/
+struct clk_pmupstate {
+	struct avfsvinobjs avfs_vinobjs;
+	struct avfsfllobjs avfs_fllobjs;
+	struct clk_domains clk_domainobjs;
+	struct clk_progs clk_progobjs;
+	struct clk_vf_points clk_vf_pointobjs;
+	struct clk_mclk_state clk_mclk;
+	struct clk_freq_controllers clk_freq_controllers;
+};
+
+struct clockentry {
+		u8 vbios_clk_domain;
+		u8 clk_which;
+		u8 perf_index;
+		u32 api_clk_domain;
+};
+
+struct set_fll_clk {
+		u32 voltuv;
+		u16 gpc2clkmhz;
+		u32 current_regime_id_gpc;
+		u32 target_regime_id_gpc;
+		u16 sys2clkmhz;
+		u32 current_regime_id_sys;
+		u32 target_regime_id_sys;
+		u16 xbar2clkmhz;
+		u32 current_regime_id_xbar;
+		u32 target_regime_id_xbar;
+};
+
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS         9
+
+struct vbios_clock_domain {
+	u8 clock_type;
+	u8 num_domains;
+	struct clockentry clock_entry[NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS];
+};
+
+struct vbios_clocks_table_1x_hal_clock_entry {
+	enum nv_pmu_clk_clkwhich domain;
+	bool b_noise_aware_capable;
+};
+
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_GPC2CLK           0
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_XBAR2CLK          1
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DRAMCLK           2
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_SYS2CLK           3
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_HUB2CLK           4
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_MSDCLK            5
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_PWRCLK            6
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DISPCLK           7
+#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_NUMCLKS           8
+
+#define PERF_CLK_MCLK           0
+#define PERF_CLK_DISPCLK        1
+#define PERF_CLK_GPC2CLK        2
+#define PERF_CLK_HOSTCLK        3
+#define PERF_CLK_LTC2CLK        4
+#define PERF_CLK_SYS2CLK        5
+#define PERF_CLK_HUB2CLK        6
+#define PERF_CLK_LEGCLK         7
+#define PERF_CLK_MSDCLK         8
+#define PERF_CLK_XCLK           9
+#define PERF_CLK_PWRCLK         10
+#define PERF_CLK_XBAR2CLK       11
+#define PERF_CLK_PCIEGENCLK     12
+#define PERF_CLK_NUM            13
+
+#define BOOT_GPC2CLK_MHZ  2581
+
+u32 clk_pmu_vin_load(struct gk20a *g);
+u32 clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain);
+u32 clk_domain_get_f_or_v(
+	struct gk20a *g,
+	u32 clkapidomain,
+	u16 *pclkmhz,
+	u32 *pvoltuv,
+	u8 railidx
+);
+u32 clk_domain_get_f_points(
+	struct gk20a *g,
+	u32 clkapidomain,
+	u32 *fpointscount,
+	u16 *freqpointsinmhz
+);
+int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
+int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
+int clk_pmu_freq_controller_load(struct gk20a *g, bool bload);
+#endif

drivers/gpu/nvgpu/clk/clk_arb.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+
+#ifndef _CLK_ARB_H_
+#define _CLK_ARB_H_
+
+struct nvgpu_clk_arb;
+struct nvgpu_clk_session;
+
+int nvgpu_clk_arb_init_arbiter(struct gk20a *g);
+
+int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+		u16 *min_mhz, u16 *max_mhz);
+
+int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
+		u32 api_domain, u16 *actual_mhz);
+
+int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
+		u32 api_domain, u16 *effective_mhz);
+
+int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
+	u32 api_domain, u32 *max_points, u16 *fpoints);
+
+u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g);
+
+void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g);
+
+int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
+		struct nvgpu_clk_session *session);
+
+int nvgpu_clk_arb_init_session(struct gk20a *g,
+		struct nvgpu_clk_session **_session);
+
+void nvgpu_clk_arb_release_session(struct gk20a *g,
+		struct nvgpu_clk_session *session);
+
+int nvgpu_clk_arb_commit_request_fd(struct gk20a *g,
+	struct nvgpu_clk_session *session, int request_fd);
+
+int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
+		int fd, u32 api_domain, u16 target_mhz);
+
+int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
+		u32 api_domain, u16 *target_mhz);
+
+int nvgpu_clk_arb_install_event_fd(struct gk20a *g,
+	struct nvgpu_clk_session *session, int *event_fd);
+
+int nvgpu_clk_arb_install_request_fd(struct gk20a *g,
+	struct nvgpu_clk_session *session, int *event_fd);
+
+void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g);
+
+int nvgpu_clk_arb_get_current_pstate(struct gk20a *g);
+
+void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
+
+#endif /* _CLK_ARB_H_ */
+

drivers/gpu/nvgpu/clk/clk_domain.h

@@ -0,0 +1,116 @@
+/*
+* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*/
+
+#ifndef _CLKDOMAIN_H_
+#define _CLKDOMAIN_H_
+
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "boardobj/boardobjgrpmask.h"
+
+struct clk_domains;
+struct clk_domain;
+
+/*data and function definition to talk to driver*/
+u32 clk_domain_sw_setup(struct gk20a *g);
+u32 clk_domain_pmu_setup(struct gk20a *g);
+
+typedef u32 clkproglink(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_domain *pdomain);
+
+typedef int clkvfsearch(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_domain *pdomain, u16 *clkmhz,
+			u32 *voltuv, u8 rail);
+
+typedef int clkgetslaveclk(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_domain *pdomain, u16 *clkmhz,
+			u16 masterclkmhz);
+
+typedef u32 clkgetfpoints(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_domain *pdomain, u32 *pfpointscount,
+			  u16 *pfreqpointsinmhz, u8 rail);
+
+struct clk_domains {
+	struct boardobjgrp_e32 super;
+	u8 n_num_entries;
+	u8 version;
+	bool b_enforce_vf_monotonicity;
+	bool b_enforce_vf_smoothening;
+	u32 vbios_domains;
+	struct boardobjgrpmask_e32 prog_domains_mask;
+	struct boardobjgrpmask_e32 master_domains_mask;
+	u16 cntr_sampling_periodms;
+	struct ctrl_clk_clk_delta  deltas;
+
+	struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+
+	struct clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+};
+
+struct clk_domain {
+	struct boardobj super;
+	u32 api_domain;
+	u32 part_mask;
+	u8 domain;
+	u8 perf_domain_index;
+	u8 perf_domain_grp_idx;
+	u8 ratio_domain;
+	u8 usage;
+	clkproglink *clkdomainclkproglink;
+	clkvfsearch *clkdomainclkvfsearch;
+	clkgetfpoints *clkdomainclkgetfpoints;
+};
+
+struct clk_domain_3x {
+	struct clk_domain super;
+	bool b_noise_aware_capable;
+};
+
+struct clk_domain_3x_fixed {
+	struct clk_domain_3x super;
+	u16  freq_mhz;
+};
+
+struct clk_domain_3x_prog {
+	struct clk_domain_3x super;
+	u8  clk_prog_idx_first;
+	u8  clk_prog_idx_last;
+	u8 noise_unaware_ordering_index;
+	u8 noise_aware_ordering_index;
+	bool b_force_noise_unaware_ordering;
+	int factory_offset_khz;
+	short freq_delta_min_mhz;
+	short freq_delta_max_mhz;
+	struct ctrl_clk_clk_delta deltas;
+};
+
+struct clk_domain_3x_master {
+	struct clk_domain_3x_prog super;
+	u32 slave_idxs_mask;
+};
+
+struct clk_domain_3x_slave {
+	struct clk_domain_3x_prog super;
+	u8 master_idx;
+	clkgetslaveclk *clkdomainclkgetslaveclk;
+};
+
+u32 clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk);
+
+#define CLK_CLK_DOMAIN_GET(pclk, idx)                                   \
+	((struct clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX(		\
+		&pclk->clk_domainobjs.super.super, (u8)(idx)))
+
+#endif

drivers/gpu/nvgpu/clk/clk_fll.c

@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "clk.h"
+#include "clk_fll.h"
+#include "include/bios.h"
+#include "boardobj/boardobjgrp.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "pmuif/gpmuifboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "gm206/bios_gm206.h"
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlvolt.h"
+#include "gk20a/pmu_gk20a.h"
+
+static u32 devinit_get_fll_device_table(struct gk20a *g,
+				   struct avfsfllobjs *pfllobjs);
+static struct fll_device *construct_fll_device(struct gk20a *g,
+		void *pargs);
+static u32 fll_device_init_pmudata_super(struct gk20a *g,
+				    struct boardobj *board_obj_ptr,
+				    struct nv_pmu_boardobj *ppmudata);
+
+static u32 _clk_fll_devgrp_pmudatainit_super(struct gk20a *g,
+					       struct boardobjgrp *pboardobjgrp,
+					       struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
+{
+	struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header *pset =
+		(struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header *)
+		pboardobjgrppmu;
+	struct avfsfllobjs *pfll_objs = (struct avfsfllobjs *)
+		pboardobjgrp;
+	u32 status = 0;
+
+	gk20a_dbg_info("");
+
+	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g), "failed to init fll pmuobjgrp");
+		return status;
+	}
+	pset->lut_num_entries = pfll_objs->lut_num_entries;
+	pset->lut_step_size_uv = pfll_objs->lut_step_size_uv;
+	pset->lut_min_voltage_uv = pfll_objs->lut_min_voltage_uv;
+	pset->max_min_freq_mhz = pfll_objs->max_min_freq_mhz;
+
+	status = boardobjgrpmask_export(
+		&pfll_objs->lut_prog_master_mask.super,
+		pfll_objs->lut_prog_master_mask.super.bitcount,
+		&pset->lut_prog_master_mask.super);
+
+	gk20a_dbg_info(" Done");
+	return status;
+}
+
+static u32 _clk_fll_devgrp_pmudata_instget(struct gk20a *g,
+					     struct nv_pmu_boardobjgrp *pmuboardobjgrp,
+					     struct nv_pmu_boardobj **ppboardobjpmudata,
+					     u8 idx)
+{
+	struct nv_pmu_clk_clk_fll_device_boardobj_grp_set  *pgrp_set =
+		(struct nv_pmu_clk_clk_fll_device_boardobj_grp_set *)
+		pmuboardobjgrp;
+
+	gk20a_dbg_info("");
+
+	/*check whether pmuboardobjgrp has a valid boardobj in index*/
+	if (((u32)BIT(idx) &
+		pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
+		return -EINVAL;
+
+	*ppboardobjpmudata = (struct nv_pmu_boardobj *)
+		&pgrp_set->objects[idx].data.board_obj;
+	gk20a_dbg_info(" Done");
+	return 0;
+}
+
+static u32 _clk_fll_devgrp_pmustatus_instget(struct gk20a *g,
+					       void *pboardobjgrppmu,
+					       struct nv_pmu_boardobj_query **ppboardobjpmustatus,
+					       u8 idx)
+{
+	struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status *pgrp_get_status =
+		(struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status *)
+		pboardobjgrppmu;
+
+	/*check whether pmuboardobjgrp has a valid boardobj in index*/
+	if (((u32)BIT(idx) &
+		pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
+		return -EINVAL;
+
+	*ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
+			&pgrp_get_status->objects[idx].data.board_obj;
+	return 0;
+}
+
+u32 clk_fll_sw_setup(struct gk20a *g)
+{
+	u32 status;
+	struct boardobjgrp *pboardobjgrp = NULL;
+	struct avfsfllobjs *pfllobjs;
+	struct fll_device *pfll;
+	struct fll_device *pfll_master;
+	struct fll_device *pfll_local;
+	u8 i;
+	u8 j;
+
+	gk20a_dbg_info("");
+
+	status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_fllobjs.super);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+		"error creating boardobjgrp for fll, status - 0x%x", status);
+		goto done;
+	}
+	pfllobjs = &(g->clk_pmu.avfs_fllobjs);
+	pboardobjgrp = &(g->clk_pmu.avfs_fllobjs.super.super);
+
+	BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, FLL_DEVICE);
+
+	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
+			clk, CLK, clk_fll_device, CLK_FLL_DEVICE);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			  "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
+			  status);
+		goto done;
+	}
+
+	pboardobjgrp->pmudatainit  = _clk_fll_devgrp_pmudatainit_super;
+	pboardobjgrp->pmudatainstget  = _clk_fll_devgrp_pmudata_instget;
+	pboardobjgrp->pmustatusinstget  = _clk_fll_devgrp_pmustatus_instget;
+	pfllobjs = (struct avfsfllobjs *)pboardobjgrp;
+	pfllobjs->lut_num_entries = CTRL_CLK_LUT_NUM_ENTRIES;
+	pfllobjs->lut_step_size_uv = CTRL_CLK_VIN_STEP_SIZE_UV;
+	pfllobjs->lut_min_voltage_uv = CTRL_CLK_LUT_MIN_VOLTAGE_UV;
+
+	/* Initialize lut prog master mask to zero.*/
+	boardobjgrpmask_e32_init(&pfllobjs->lut_prog_master_mask, NULL);
+
+	status = devinit_get_fll_device_table(g, pfllobjs);
+	if (status)
+		goto done;
+
+	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
+				&g->clk_pmu.avfs_fllobjs.super.super,
+				clk, CLK, clk_fll_device, CLK_FLL_DEVICE);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			  "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
+			  status);
+		goto done;
+	}
+
+	BOARDOBJGRP_FOR_EACH(&(pfllobjs->super.super),
+			     struct fll_device *, pfll, i) {
+		pfll_master = NULL;
+		j = 0;
+		BOARDOBJGRP_ITERATOR(&(pfllobjs->super.super),
+				     struct fll_device *, pfll_local, j,
+				     &pfllobjs->lut_prog_master_mask.super) {
+			if (pfll_local->clk_domain == pfll->clk_domain) {
+				pfll_master = pfll_local;
+				break;
+			}
+		}
+
+		if (pfll_master == NULL) {
+			status = boardobjgrpmask_bitset(
+				&pfllobjs->lut_prog_master_mask.super,
+				BOARDOBJ_GET_IDX(pfll));
+			if (status) {
+				gk20a_err(dev_from_gk20a(g), "err setting lutprogmask");
+				goto done;
+			}
+			pfll_master = pfll;
+		}
+		status = pfll_master->lut_broadcast_slave_register(
+			g, pfllobjs, pfll_master, pfll);
+
+		if (status) {
+			gk20a_err(dev_from_gk20a(g), "err setting lutslavemask");
+			goto done;
+		}
+	}
+done:
+	gk20a_dbg_info(" done status %x", status);
+	return status;
+}
+
+u32 clk_fll_pmu_setup(struct gk20a *g)
+{
+	u32 status;
+	struct boardobjgrp *pboardobjgrp = NULL;
+
+	gk20a_dbg_info("");
+
+	pboardobjgrp = &g->clk_pmu.avfs_fllobjs.super.super;
+
+	if (!pboardobjgrp->bconstructed)
+		return -EINVAL;
+
+	status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
+
+	gk20a_dbg_info("Done");
+	return status;
+}
+
+static u32 devinit_get_fll_device_table(struct gk20a *g,
+				   struct avfsfllobjs *pfllobjs)
+{
+	u32 status = 0;
+	u8 *fll_table_ptr = NULL;
+	struct fll_descriptor_header fll_desc_table_header_sz = { 0 };
+	struct fll_descriptor_header_10 fll_desc_table_header = { 0 };
+	struct fll_descriptor_entry_10 fll_desc_table_entry = { 0 };
+	u8 *fll_tbl_entry_ptr = NULL;
+	u32 index = 0;
+	struct fll_device fll_dev_data;
+	struct fll_device *pfll_dev;
+	struct vin_device *pvin_dev;
+	u32 desctablesize;
+	u32 vbios_domain = NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP;
+	struct avfsvinobjs *pvinobjs = &g->clk_pmu.avfs_vinobjs;
+
+	gk20a_dbg_info("");
+
+	if (g->ops.bios.get_perf_table_ptrs) {
+		fll_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
+				  g->bios.clock_token, FLL_TABLE);
+		if (fll_table_ptr == NULL) {
+			status = -1;
+			goto done;
+		}
+	}
+
+	memcpy(&fll_desc_table_header_sz, fll_table_ptr,
+			sizeof(struct fll_descriptor_header));
+	if (fll_desc_table_header_sz.size >= FLL_DESCRIPTOR_HEADER_10_SIZE_6)
+		desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_6;
+	else
+		desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_4;
+
+	memcpy(&fll_desc_table_header, fll_table_ptr, desctablesize);
+
+	if (desctablesize == FLL_DESCRIPTOR_HEADER_10_SIZE_6)
+		pfllobjs->max_min_freq_mhz =
+			fll_desc_table_header.max_min_freq_mhz;
+	else
+		pfllobjs->max_min_freq_mhz = 0;
+
+	/* Read table entries*/
+	fll_tbl_entry_ptr = fll_table_ptr + desctablesize;
+	for (index = 0; index < fll_desc_table_header.entry_count; index++) {
+		u32 fll_id;
+
+		memcpy(&fll_desc_table_entry, fll_tbl_entry_ptr,
+				sizeof(struct fll_descriptor_entry_10));
+
+		if (fll_desc_table_entry.fll_device_type == CTRL_CLK_FLL_TYPE_DISABLED)
+			continue;
+
+		fll_id = fll_desc_table_entry.fll_device_id;
+
+		pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs,
+				(u8)fll_desc_table_entry.vin_idx_logic);
+		if (pvin_dev == NULL)
+			return -EINVAL;
+
+		pvin_dev->flls_shared_mask |= BIT(fll_id);
+
+		pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs,
+				(u8)fll_desc_table_entry.vin_idx_sram);
+		if (pvin_dev == NULL)
+			return -EINVAL;
+
+		pvin_dev->flls_shared_mask |= BIT(fll_id);
+
+		fll_dev_data.super.type =
+			(u8)fll_desc_table_entry.fll_device_type;
+		fll_dev_data.id = (u8)fll_desc_table_entry.fll_device_id;
+		fll_dev_data.mdiv = (u8)BIOS_GET_FIELD(
+			fll_desc_table_entry.fll_params,
+			NV_FLL_DESC_FLL_PARAMS_MDIV);
+		fll_dev_data.input_freq_mhz =
+			(u16)fll_desc_table_entry.ref_freq_mhz;
+		fll_dev_data.min_freq_vfe_idx =
+			(u8)fll_desc_table_entry.min_freq_vfe_idx;
+		fll_dev_data.freq_ctrl_idx = CTRL_BOARDOBJ_IDX_INVALID;
+
+		vbios_domain = (u32)(fll_desc_table_entry.clk_domain &
+					NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK);
+		if (vbios_domain == 0)
+			fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_GPC2CLK;
+		else if (vbios_domain == 1)
+			fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_XBAR2CLK;
+		else if (vbios_domain == 3)
+			fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_SYS2CLK;
+		else
+			continue;
+
+		fll_dev_data.rail_idx_for_lut = 0;
+
+		fll_dev_data.vin_idx_logic =
+			(u8)fll_desc_table_entry.vin_idx_logic;
+		fll_dev_data.vin_idx_sram =
+			(u8)fll_desc_table_entry.vin_idx_sram;
+		fll_dev_data.lut_device.vselect_mode =
+			(u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params,
+					   NV_FLL_DESC_LUT_PARAMS_VSELECT);
+		fll_dev_data.lut_device.hysteresis_threshold =
+			(u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params,
+					   NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD);
+		fll_dev_data.regime_desc.regime_id =
+			CTRL_CLK_FLL_REGIME_ID_FFR;
+		fll_dev_data.regime_desc.fixed_freq_regime_limit_mhz =
+			(u16)fll_desc_table_entry.ffr_cutoff_freq_mhz;
+
+		/*construct fll device*/
+		pfll_dev = construct_fll_device(g, (void *)&fll_dev_data);
+
+		status = boardobjgrp_objinsert(&pfllobjs->super.super,
+				(struct boardobj *)pfll_dev, index);
+
+		fll_tbl_entry_ptr += fll_desc_table_header.entry_size;
+	}
+
+done:
+	gk20a_dbg_info(" done status %x", status);
+	return status;
+}
+
+static u32 lutbroadcastslaveregister(struct gk20a *g,
+				     struct avfsfllobjs *pfllobjs,
+				     struct fll_device *pfll,
+				     struct fll_device *pfll_slave)
+{
+	if (pfll->clk_domain != pfll_slave->clk_domain)
+		return -EINVAL;
+
+	return boardobjgrpmask_bitset(&pfll->
+		lut_prog_broadcast_slave_mask.super,
+		BOARDOBJ_GET_IDX(pfll_slave));
+}
+
+static struct fll_device *construct_fll_device(struct gk20a *g,
+		void *pargs)
+{
+	struct boardobj *board_obj_ptr = NULL;
+	struct fll_device *pfll_dev;
+	struct fll_device *board_obj_fll_ptr = NULL;
+	u32 status;
+
+	gk20a_dbg_info("");
+	status = boardobj_construct_super(g, &board_obj_ptr,
+		sizeof(struct fll_device), pargs);
+	if (status)
+		return NULL;
+
+	pfll_dev = (struct fll_device *)pargs;
+	board_obj_fll_ptr = (struct fll_device *)board_obj_ptr;
+	board_obj_ptr->pmudatainit  = fll_device_init_pmudata_super;
+	board_obj_fll_ptr->lut_broadcast_slave_register =
+		lutbroadcastslaveregister;
+	board_obj_fll_ptr->id = pfll_dev->id;
+	board_obj_fll_ptr->mdiv = pfll_dev->mdiv;
+	board_obj_fll_ptr->rail_idx_for_lut = pfll_dev->rail_idx_for_lut;
+	board_obj_fll_ptr->input_freq_mhz = pfll_dev->input_freq_mhz;
+	board_obj_fll_ptr->clk_domain = pfll_dev->clk_domain;
+	board_obj_fll_ptr->vin_idx_logic = pfll_dev->vin_idx_logic;
+	board_obj_fll_ptr->vin_idx_sram = pfll_dev->vin_idx_sram;
+	board_obj_fll_ptr->min_freq_vfe_idx =
+		pfll_dev->min_freq_vfe_idx;
+	board_obj_fll_ptr->freq_ctrl_idx = pfll_dev->freq_ctrl_idx;
+	memcpy(&board_obj_fll_ptr->lut_device, &pfll_dev->lut_device,
+		sizeof(struct nv_pmu_clk_lut_device_desc));
+	memcpy(&board_obj_fll_ptr->regime_desc, &pfll_dev->regime_desc,
+		sizeof(struct nv_pmu_clk_regime_desc));
+	boardobjgrpmask_e32_init(
+		&board_obj_fll_ptr->lut_prog_broadcast_slave_mask, NULL);
+
+	gk20a_dbg_info(" Done");
+
+	return (struct fll_device *)board_obj_ptr;
+}
+
+static u32 fll_device_init_pmudata_super(struct gk20a *g,
+				    struct boardobj *board_obj_ptr,
+				    struct nv_pmu_boardobj *ppmudata)
+{
+	u32 status = 0;
+	struct fll_device *pfll_dev;
+	struct nv_pmu_clk_clk_fll_device_boardobj_set *perf_pmu_data;
+
+	gk20a_dbg_info("");
+
+	status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
+	if (status != 0)
+		return status;
+
+	pfll_dev = (struct fll_device *)board_obj_ptr;
+	perf_pmu_data = (struct nv_pmu_clk_clk_fll_device_boardobj_set *)
+		ppmudata;
+
+	perf_pmu_data->id = pfll_dev->id;
+	perf_pmu_data->mdiv = pfll_dev->mdiv;
+	perf_pmu_data->rail_idx_for_lut = pfll_dev->rail_idx_for_lut;
+	perf_pmu_data->input_freq_mhz = pfll_dev->input_freq_mhz;
+	perf_pmu_data->vin_idx_logic = pfll_dev->vin_idx_logic;
+	perf_pmu_data->vin_idx_sram = pfll_dev->vin_idx_sram;
+	perf_pmu_data->clk_domain = pfll_dev->clk_domain;
+	perf_pmu_data->min_freq_vfe_idx =
+		pfll_dev->min_freq_vfe_idx;
+	perf_pmu_data->freq_ctrl_idx = pfll_dev->freq_ctrl_idx;
+
+	memcpy(&perf_pmu_data->lut_device, &pfll_dev->lut_device,
+		sizeof(struct nv_pmu_clk_lut_device_desc));
+	memcpy(&perf_pmu_data->regime_desc, &pfll_dev->regime_desc,
+		sizeof(struct nv_pmu_clk_regime_desc));
+
+	status = boardobjgrpmask_export(
+		&pfll_dev->lut_prog_broadcast_slave_mask.super,
+		pfll_dev->lut_prog_broadcast_slave_mask.super.bitcount,
+		&perf_pmu_data->lut_prog_broadcast_slave_mask.super);
+
+	gk20a_dbg_info(" Done");
+
+	return status;
+}

drivers/gpu/nvgpu/clk/clk_fll.h

@@ -0,0 +1,68 @@
+/*
+* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*/
+
+#ifndef _CLKFLL_H_
+#define _CLKFLL_H_
+
+#include "pmuif/gpmuifclk.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "boardobj/boardobjgrpmask.h"
+
+/*data and function definition to talk to driver*/
+u32 clk_fll_sw_setup(struct gk20a *g);
+u32 clk_fll_pmu_setup(struct gk20a *g);
+
+struct avfsfllobjs {
+	struct boardobjgrp_e32 super;
+	struct boardobjgrpmask_e32 lut_prog_master_mask;
+	u32 lut_step_size_uv;
+	u32 lut_min_voltage_uv;
+	u8 lut_num_entries;
+	u16 max_min_freq_mhz;
+};
+
+struct fll_device;
+
+typedef u32 fll_lut_broadcast_slave_register(struct gk20a *g,
+	struct avfsfllobjs *pfllobjs,
+	struct fll_device *pfll,
+	struct fll_device *pfll_slave);
+
+struct fll_device {
+	struct boardobj super;
+	u8 id;
+	u8 mdiv;
+	u16 input_freq_mhz;
+	u32 clk_domain;
+	u8 vin_idx_logic;
+	u8 vin_idx_sram;
+	u8 rail_idx_for_lut;
+	struct nv_pmu_clk_lut_device_desc lut_device;
+	struct nv_pmu_clk_regime_desc regime_desc;
+	u8 min_freq_vfe_idx;
+	u8 freq_ctrl_idx;
+	u8 target_regime_id_override;
+	struct boardobjgrpmask_e32 lut_prog_broadcast_slave_mask;
+	fll_lut_broadcast_slave_register *lut_broadcast_slave_register;
+};
+
+#define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \
+	(pclk->avfs_fllobjs.lut_num_entries)
+
+#define CLK_FLL_LUT_MIN_VOLTAGE_UV(pclk) \
+	(pclk->avfs_fllobjs.lut_min_voltage_uv)
+#define CLK_FLL_LUT_STEP_SIZE_UV(pclk) \
+	(pclk->avfs_fllobjs.lut_step_size_uv)
+
+#endif
+

drivers/gpu/nvgpu/clk/clk_freq_controller.c

@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "clk.h"
+#include "clk_fll.h"
+#include "clk_domain.h"
+#include "clk_freq_controller.h"
+#include "include/bios.h"
+#include "boardobj/boardobjgrp.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "pmuif/gpmuifboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "gm206/bios_gm206.h"
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlvolt.h"
+#include "gk20a/pmu_gk20a.h"
+
+static u32 clk_freq_controller_pmudatainit_super(struct gk20a *g,
+	struct boardobj *board_obj_ptr,
+	struct nv_pmu_boardobj *ppmudata)
+{
+	struct nv_pmu_clk_clk_freq_controller_boardobj_set *pfreq_cntlr_set;
+	struct clk_freq_controller *pfreq_cntlr;
+	u32 status = 0;
+
+	status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
+	if (status)
+		return status;
+
+	pfreq_cntlr_set =
+		(struct nv_pmu_clk_clk_freq_controller_boardobj_set *)ppmudata;
+	pfreq_cntlr    = (struct clk_freq_controller *)board_obj_ptr;
+
+	pfreq_cntlr_set->controller_id = pfreq_cntlr->controller_id;
+	pfreq_cntlr_set->clk_domain = pfreq_cntlr->clk_domain;
+	pfreq_cntlr_set->parts_freq_mode = pfreq_cntlr->parts_freq_mode;
+	pfreq_cntlr_set->bdisable = pfreq_cntlr->bdisable;
+	pfreq_cntlr_set->freq_cap_noise_unaware_vmin_above =
+		pfreq_cntlr->freq_cap_noise_unaware_vmin_above;
+	pfreq_cntlr_set->freq_cap_noise_unaware_vmin_below =
+		pfreq_cntlr->freq_cap_noise_unaware_vmin_below;
+	pfreq_cntlr_set->freq_hyst_pos_mhz = pfreq_cntlr->freq_hyst_pos_mhz;
+	pfreq_cntlr_set->freq_hyst_neg_mhz = pfreq_cntlr->freq_hyst_neg_mhz;
+
+	return status;
+}
+
+static u32 clk_freq_controller_pmudatainit_pi(struct gk20a *g,
+	struct boardobj *board_obj_ptr,
+	struct nv_pmu_boardobj *ppmudata)
+{
+	struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set
+		*pfreq_cntlr_pi_set;
+	struct clk_freq_controller_pi *pfreq_cntlr_pi;
+	u32 status = 0;
+
+	status = clk_freq_controller_pmudatainit_super(g,
+		board_obj_ptr, ppmudata);
+	if (status)
+		return -1;
+
+	pfreq_cntlr_pi_set =
+		(struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set *)
+		ppmudata;
+	pfreq_cntlr_pi = (struct clk_freq_controller_pi *)board_obj_ptr;
+
+	pfreq_cntlr_pi_set->prop_gain = pfreq_cntlr_pi->prop_gain;
+	pfreq_cntlr_pi_set->integ_gain = pfreq_cntlr_pi->integ_gain;
+	pfreq_cntlr_pi_set->integ_decay = pfreq_cntlr_pi->integ_decay;
+	pfreq_cntlr_pi_set->volt_delta_min = pfreq_cntlr_pi->volt_delta_min;
+	pfreq_cntlr_pi_set->volt_delta_max = pfreq_cntlr_pi->volt_delta_max;
+	pfreq_cntlr_pi_set->slowdown_pct_min = pfreq_cntlr_pi->slowdown_pct_min;
+	pfreq_cntlr_pi_set->bpoison = pfreq_cntlr_pi->bpoison;
+
+	return status;
+}
+
+static u32 clk_freq_controller_construct_super(struct gk20a *g,
+	struct boardobj **ppboardobj,
+	u16 size, void *pargs)
+{
+	struct clk_freq_controller *pfreq_cntlr = NULL;
+	struct clk_freq_controller *pfreq_cntlr_tmp = NULL;
+	u32 status = 0;
+
+	status = boardobj_construct_super(g, ppboardobj, size, pargs);
+	if (status)
+		return -EINVAL;
+
+	pfreq_cntlr_tmp = (struct clk_freq_controller *)pargs;
+	pfreq_cntlr = (struct clk_freq_controller *)*ppboardobj;
+
+	pfreq_cntlr->super.pmudatainit = clk_freq_controller_pmudatainit_super;
+
+	pfreq_cntlr->controller_id   = pfreq_cntlr_tmp->controller_id;
+	pfreq_cntlr->clk_domain      = pfreq_cntlr_tmp->clk_domain;
+	pfreq_cntlr->parts_freq_mode  = pfreq_cntlr_tmp->parts_freq_mode;
+	pfreq_cntlr->freq_cap_noise_unaware_vmin_above  =
+		pfreq_cntlr_tmp->freq_cap_noise_unaware_vmin_above;
+	pfreq_cntlr->freq_cap_noise_unaware_vmin_below  =
+		pfreq_cntlr_tmp->freq_cap_noise_unaware_vmin_below;
+	pfreq_cntlr->freq_hyst_pos_mhz = pfreq_cntlr_tmp->freq_hyst_pos_mhz;
+	pfreq_cntlr->freq_hyst_neg_mhz = pfreq_cntlr_tmp->freq_hyst_neg_mhz;
+
+	return status;
+}
+
+static u32 clk_freq_controller_construct_pi(struct gk20a *g,
+	struct boardobj **ppboardobj,
+	u16 size, void *pargs)
+{
+	struct clk_freq_controller_pi *pfreq_cntlr_pi = NULL;
+	struct clk_freq_controller_pi *pfreq_cntlr_pi_tmp = NULL;
+	u32 status = 0;
+
+	status = clk_freq_controller_construct_super(g, ppboardobj,
+			size, pargs);
+	if (status)
+		return -EINVAL;
+
+	pfreq_cntlr_pi = (struct clk_freq_controller_pi *)*ppboardobj;
+	pfreq_cntlr_pi_tmp = (struct clk_freq_controller_pi *)pargs;
+
+	pfreq_cntlr_pi->super.super.pmudatainit =
+		clk_freq_controller_pmudatainit_pi;
+
+	pfreq_cntlr_pi->prop_gain = pfreq_cntlr_pi_tmp->prop_gain;
+	pfreq_cntlr_pi->integ_gain = pfreq_cntlr_pi_tmp->integ_gain;
+	pfreq_cntlr_pi->integ_decay = pfreq_cntlr_pi_tmp->integ_decay;
+	pfreq_cntlr_pi->volt_delta_min = pfreq_cntlr_pi_tmp->volt_delta_min;
+	pfreq_cntlr_pi->volt_delta_max = pfreq_cntlr_pi_tmp->volt_delta_max;
+	pfreq_cntlr_pi->slowdown_pct_min = pfreq_cntlr_pi_tmp->slowdown_pct_min;
+	pfreq_cntlr_pi->bpoison = pfreq_cntlr_pi_tmp->bpoison;
+
+	return status;
+}
+
+struct clk_freq_controller *clk_clk_freq_controller_construct(struct gk20a *g,
+	void *pargs)
+{
+	struct boardobj *board_obj_ptr = NULL;
+	u32 status = 0;
+
+	if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI)
+		return NULL;
+
+	status = clk_freq_controller_construct_pi(g, &board_obj_ptr,
+				sizeof(struct clk_freq_controller_pi), pargs);
+	if (status)
+		return NULL;
+
+	return (struct clk_freq_controller *)board_obj_ptr;
+}
+
+
+static u32 clk_get_freq_controller_table(struct gk20a *g,
+		struct clk_freq_controllers *pclk_freq_controllers)
+{
+	u32 status = 0;
+	u8 *pfreq_controller_table_ptr = NULL;
+	struct vbios_fct_1x_header header = { 0 };
+	struct vbios_fct_1x_entry entry  = { 0 };
+	u8 entry_idx;
+	u8 *entry_offset;
+	u32 freq_controller_id;
+	struct clk_freq_controller *pclk_freq_cntr = NULL;
+	struct clk_freq_controller *ptmp_freq_cntr = NULL;
+	struct clk_freq_controller_pi *ptmp_freq_cntr_pi = NULL;
+	struct clk_domain *pclk_domain;
+
+	struct freq_controller_data_type {
+		union {
+			struct boardobj board_obj;
+			struct clk_freq_controller freq_controller;
+			struct clk_freq_controller_pi  freq_controller_pi;
+		};
+	} freq_controller_data;
+
+	if (g->ops.bios.get_perf_table_ptrs) {
+		pfreq_controller_table_ptr =
+			(u8 *)g->ops.bios.get_perf_table_ptrs(g,
+				g->bios.clock_token,
+				FREQUENCY_CONTROLLER_TABLE);
+		if (pfreq_controller_table_ptr == NULL) {
+			status = -EINVAL;
+			goto done;
+		}
+	} else {
+		status = -EINVAL;
+		goto done;
+	}
+
+	memcpy(&header, pfreq_controller_table_ptr,
+			sizeof(struct vbios_fct_1x_header));
+
+	pclk_freq_controllers->sampling_period_ms = header.sampling_period_ms;
+	pclk_freq_controllers->volt_policy_idx = 0;
+
+	/* Read in the entries. */
+	for (entry_idx = 0; entry_idx < header.entry_count; entry_idx++) {
+		entry_offset = (pfreq_controller_table_ptr +
+			header.header_size + (entry_idx * header.entry_size));
+
+		memset(&freq_controller_data, 0x0,
+				sizeof(struct freq_controller_data_type));
+		ptmp_freq_cntr = &freq_controller_data.freq_controller;
+		ptmp_freq_cntr_pi = &freq_controller_data.freq_controller_pi;
+
+		memcpy(&entry, entry_offset,
+			sizeof(struct vbios_fct_1x_entry));
+
+		if (!BIOS_GET_FIELD(entry.flags0,
+				NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE))
+			continue;
+
+		freq_controller_data.board_obj.type = (u8)BIOS_GET_FIELD(
+			entry.flags0, NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE);
+
+		ptmp_freq_cntr->controller_id =
+			(u8)BIOS_GET_FIELD(entry.param0,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID);
+
+		freq_controller_id = ptmp_freq_cntr->controller_id;
+
+		pclk_domain = CLK_CLK_DOMAIN_GET((&g->clk_pmu),
+				(u32)entry.clk_domain_idx);
+		freq_controller_data.freq_controller.clk_domain =
+			pclk_domain->api_domain;
+
+		ptmp_freq_cntr->parts_freq_mode =
+			(u8)BIOS_GET_FIELD(entry.param0,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE);
+
+		/* Populate PI specific data */
+		ptmp_freq_cntr_pi->slowdown_pct_min =
+			(u8)BIOS_GET_FIELD(entry.param1,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN);
+
+		ptmp_freq_cntr_pi->bpoison =
+			BIOS_GET_FIELD(entry.param1,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON);
+
+		ptmp_freq_cntr_pi->prop_gain =
+			(s32)BIOS_GET_FIELD(entry.param2,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN);
+
+		ptmp_freq_cntr_pi->integ_gain =
+			(s32)BIOS_GET_FIELD(entry.param3,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN);
+
+		ptmp_freq_cntr_pi->integ_decay =
+			(s32)BIOS_GET_FIELD(entry.param4,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY);
+
+		ptmp_freq_cntr_pi->volt_delta_min =
+		(s32)BIOS_GET_FIELD(entry.param5,
+			NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN);
+
+		ptmp_freq_cntr_pi->volt_delta_max =
+		(s32)BIOS_GET_FIELD(entry.param6,
+			NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX);
+
+		ptmp_freq_cntr->freq_cap_noise_unaware_vmin_above =
+			(s16)BIOS_GET_FIELD(entry.param7,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF);
+
+		ptmp_freq_cntr->freq_cap_noise_unaware_vmin_below =
+		(s16)BIOS_GET_FIELD(entry.param7,
+			NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN);
+
+		ptmp_freq_cntr->freq_hyst_pos_mhz =
+			(s16)BIOS_GET_FIELD(entry.param8,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS);
+		ptmp_freq_cntr->freq_hyst_neg_mhz =
+			(s16)BIOS_GET_FIELD(entry.param8,
+				NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG);
+
+		if (ptmp_freq_cntr_pi->volt_delta_max <
+			ptmp_freq_cntr_pi->volt_delta_min)
+			goto done;
+
+		pclk_freq_cntr = clk_clk_freq_controller_construct(g,
+						(void *)&freq_controller_data);
+
+		if (pclk_freq_cntr == NULL) {
+			gk20a_err(dev_from_gk20a(g),
+				"unable to construct clock freq cntlr boardobj for %d",
+				entry_idx);
+			status = -EINVAL;
+			goto done;
+		}
+
+		status = boardobjgrp_objinsert(
+				&pclk_freq_controllers->super.super,
+				(struct boardobj *)pclk_freq_cntr, entry_idx);
+		if (status) {
+			gk20a_err(dev_from_gk20a(g),
+			"unable to insert clock freq cntlr boardobj for");
+			status = -EINVAL;
+			goto done;
+		}
+
+	}
+
+done:
+	return status;
+}
+
+u32 clk_freq_controller_pmu_setup(struct gk20a *g)
+{
+	u32 status;
+	struct boardobjgrp *pboardobjgrp = NULL;
+
+	gk20a_dbg_info("");
+
+	pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super;
+
+	if (!pboardobjgrp->bconstructed)
+		return -EINVAL;
+
+	status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
+
+	gk20a_dbg_info("Done");
+	return status;
+}
+
+static u32 _clk_freq_controller_devgrp_pmudata_instget(struct gk20a *g,
+				   struct nv_pmu_boardobjgrp *pmuboardobjgrp,
+				   struct nv_pmu_boardobj **ppboardobjpmudata,
+					   u8 idx)
+{
+	struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set *pgrp_set =
+		(struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set *)
+		pmuboardobjgrp;
+
+	gk20a_dbg_info("");
+
+	/*check whether pmuboardobjgrp has a valid boardobj in index*/
+	if (((u32)BIT(idx) &
+		pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
+		return -EINVAL;
+
+	*ppboardobjpmudata = (struct nv_pmu_boardobj *)
+		&pgrp_set->objects[idx].data.board_obj;
+	gk20a_dbg_info(" Done");
+	return 0;
+}
+
+static u32 _clk_freq_controllers_pmudatainit(struct gk20a *g,
+			 struct boardobjgrp *pboardobjgrp,
+			 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
+{
+	struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header *pset =
+		(struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header *)
+		pboardobjgrppmu;
+	struct clk_freq_controllers *pcntrs =
+		(struct clk_freq_controllers *)pboardobjgrp;
+	u32 status = 0;
+
+	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"error updating pmu boardobjgrp for clk freq ctrs 0x%x",
+			 status);
+		goto done;
+	}
+	pset->sampling_period_ms = pcntrs->sampling_period_ms;
+	pset->volt_policy_idx = pcntrs->volt_policy_idx;
+
+done:
+	return status;
+}
+
+u32 clk_freq_controller_sw_setup(struct gk20a *g)
+{
+	u32 status = 0;
+	struct boardobjgrp *pboardobjgrp = NULL;
+	struct clk_freq_controllers *pclk_freq_controllers;
+	struct avfsfllobjs *pfllobjs = &(g->clk_pmu.avfs_fllobjs);
+	struct fll_device *pfll;
+	struct clk_freq_controller *pclkfreqctrl;
+	u8 i;
+	u8 j;
+
+	gk20a_dbg_info("");
+
+	pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
+	status = boardobjgrpconstruct_e32(&pclk_freq_controllers->super);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"error creating boardobjgrp for clk FCT, status - 0x%x",
+			status);
+		goto done;
+	}
+
+	pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super;
+
+	pboardobjgrp->pmudatainit  = _clk_freq_controllers_pmudatainit;
+	pboardobjgrp->pmudatainstget  =
+			_clk_freq_controller_devgrp_pmudata_instget;
+	pboardobjgrp->pmustatusinstget  = NULL;
+
+	/* Initialize mask to zero.*/
+	boardobjgrpmask_e32_init(&pclk_freq_controllers->freq_ctrl_load_mask,
+		NULL);
+
+	BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_FREQ_CONTROLLER);
+
+	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
+			clk, CLK, clk_freq_controller, CLK_FREQ_CONTROLLER);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			  "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
+			  status);
+		goto done;
+	}
+
+	status = clk_get_freq_controller_table(g, pclk_freq_controllers);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"error reading freq controller table - 0x%x",
+			status);
+		goto done;
+	}
+
+	BOARDOBJGRP_FOR_EACH(&(pclk_freq_controllers->super.super),
+			     struct clk_freq_controller *, pclkfreqctrl, i) {
+		pfll = NULL;
+		j = 0;
+		BOARDOBJGRP_FOR_EACH(&(pfllobjs->super.super),
+			     struct fll_device *, pfll, j) {
+			if (pclkfreqctrl->controller_id == pfll->id) {
+				pfll->freq_ctrl_idx = i;
+				break;
+			}
+		}
+		boardobjgrpmask_bitset(&pclk_freq_controllers->
+			freq_ctrl_load_mask.super, i);
+	}
+done:
+		gk20a_dbg_info(" done status %x", status);
+		return status;
+}

drivers/gpu/nvgpu/clk/clk_freq_controller.h

@@ -0,0 +1,74 @@
+/*
+* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*/
+
+#ifndef _CLK_FREQ_CONTROLLER_H_
+#define _CLK_FREQ_CONTROLLER_H_
+
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS  0x00
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC  0x01
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR 0x02
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0 0x03
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1 0x04
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2 0x05
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3 0x06
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4 0x07
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5 0x08
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPCS 0x09
+
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_MASK_UNICAST_GPC     \
+			(BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0) | \
+			BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1) | \
+			BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2) | \
+			BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3) | \
+			BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4) | \
+			BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5))
+
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_DISABLED  0x00
+#define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI        0x01
+
+
+struct clk_freq_controller {
+	struct boardobj    super;
+	u8   controller_id;
+	u8   parts_freq_mode;
+	bool bdisable;
+	u32  clk_domain;
+	s16  freq_cap_noise_unaware_vmin_above;
+	s16  freq_cap_noise_unaware_vmin_below;
+	s16  freq_hyst_pos_mhz;
+	s16  freq_hyst_neg_mhz;
+};
+
+struct clk_freq_controller_pi {
+	struct clk_freq_controller super;
+	s32 prop_gain;
+	s32 integ_gain;
+	s32 integ_decay;
+	s32 volt_delta_min;
+	s32 volt_delta_max;
+	u8  slowdown_pct_min;
+	bool bpoison;
+};
+
+struct clk_freq_controllers {
+	struct boardobjgrp_e32 super;
+	u32 sampling_period_ms;
+	struct boardobjgrpmask_e32 freq_ctrl_load_mask;
+	u8 volt_policy_idx;
+	void *pprereq_load;
+};
+
+u32 clk_freq_controller_sw_setup(struct gk20a *g);
+u32 clk_freq_controller_pmu_setup(struct gk20a *g);
+
+#endif

drivers/gpu/nvgpu/clk/clk_mclk.h

@@ -0,0 +1,52 @@
+/*
+* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*/
+
+#ifndef _CLKMCLK_H_
+#define _CLKMCLK_H_
+
+#include <linux/mutex.h>
+
+enum gk20a_mclk_speed {
+	gk20a_mclk_low_speed,
+	gk20a_mclk_mid_speed,
+	gk20a_mclk_high_speed,
+};
+
+struct clk_mclk_state {
+	enum gk20a_mclk_speed speed;
+	struct mutex mclk_lock;
+	struct mutex data_lock;
+
+	u16 p5_min;
+	u16 p0_min;
+
+	void *vreg_buf;
+	bool init;
+
+	/* function pointers */
+	int (*change)(struct gk20a *g, u16 val);
+
+#ifdef CONFIG_DEBUG_FS
+	s64 switch_max;
+	s64 switch_min;
+	u64 switch_num;
+	s64 switch_avg;
+	s64 switch_std;
+	bool debugfs_set;
+#endif
+};
+
+int clk_mclkseq_init_mclk_gddr5(struct gk20a *g);
+int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val);
+
+#endif

drivers/gpu/nvgpu/clk/clk_prog.h

@@ -0,0 +1,90 @@
+/*
+* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*/
+
+#ifndef _CLKPROG_H_
+#define _CLKPROG_H_
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "boardobj/boardobjgrpmask.h"
+
+u32 clk_prog_sw_setup(struct gk20a *g);
+u32 clk_prog_pmu_setup(struct gk20a *g);
+struct clk_prog_1x_master;
+
+typedef u32 vf_flatten(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_prog_1x_master *p1xmaster,
+			u8 clk_domain_idx, u16 *pfreqmaxlastmhz);
+
+typedef u32 vf_lookup(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_prog_1x_master *p1xmaster,
+			u8 *slave_clk_domain_idx, u16 *pclkmhz,
+			u32 *pvoltuv, u8 rail);
+
+typedef int get_slaveclk(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_prog_1x_master *p1xmaster,
+			u8 slave_clk_domain_idx, u16 *pclkmhz,
+			u16 masterclkmhz);
+
+typedef u32 get_fpoints(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_prog_1x_master *p1xmaster,
+			u32 *pfpointscount,
+			u16 **ppfreqpointsinmhz, u8 rail);
+
+
+struct clk_progs {
+	struct boardobjgrp_e255 super;
+	u8 slave_entry_count;
+	u8 vf_entry_count;
+
+};
+
+struct clk_prog {
+	struct boardobj super;
+};
+
+struct clk_prog_1x {
+	struct clk_prog super;
+	u8  source;
+	u16 freq_max_mhz;
+	union ctrl_clk_clk_prog_1x_source_data source_data;
+};
+
+struct clk_prog_1x_master {
+	struct clk_prog_1x super;
+	bool b_o_c_o_v_enabled;
+	struct ctrl_clk_clk_prog_1x_master_vf_entry *p_vf_entries;
+	struct ctrl_clk_clk_delta deltas;
+	union ctrl_clk_clk_prog_1x_master_source_data source_data;
+	vf_flatten *vfflatten;
+	vf_lookup *vflookup;
+	get_fpoints *getfpoints;
+	get_slaveclk *getslaveclk;
+};
+
+struct clk_prog_1x_master_ratio {
+	struct clk_prog_1x_master super;
+	struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *p_slave_entries;
+};
+
+struct clk_prog_1x_master_table {
+	struct clk_prog_1x_master super;
+	struct ctrl_clk_clk_prog_1x_master_table_slave_entry *p_slave_entries;
+};
+
+#define CLK_CLK_PROG_GET(pclk, idx)                                            \
+	((struct clk_prog *)BOARDOBJGRP_OBJ_GET_BY_IDX(			\
+		&pclk->clk_progobjs.super.super, (u8)(idx)))
+
+#endif

drivers/gpu/nvgpu/clk/clk_vf_point.c

@@ -0,0 +1,418 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "clk.h"
+#include "clk_vf_point.h"
+#include "include/bios.h"
+#include "boardobj/boardobjgrp.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "pmuif/gpmuifboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "gm206/bios_gm206.h"
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlvolt.h"
+#include "gk20a/pmu_gk20a.h"
+
+static u32 _clk_vf_point_pmudatainit_super(struct gk20a *g, struct boardobj
+	*board_obj_ptr,	struct nv_pmu_boardobj *ppmudata);
+
+static u32 _clk_vf_points_pmudatainit(struct gk20a *g,
+				      struct boardobjgrp *pboardobjgrp,
+				      struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
+{
+	u32 status = 0;
+
+	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			  "error updating pmu boardobjgrp for clk vfpoint 0x%x",
+			  status);
+		goto done;
+	}
+
+done:
+	return status;
+}
+
+static u32 _clk_vf_points_pmudata_instget(struct gk20a *g,
+					  struct nv_pmu_boardobjgrp *pmuboardobjgrp,
+					  struct nv_pmu_boardobj **ppboardobjpmudata,
+					  u8 idx)
+{
+	struct nv_pmu_clk_clk_vf_point_boardobj_grp_set  *pgrp_set =
+		(struct nv_pmu_clk_clk_vf_point_boardobj_grp_set *)
+		pmuboardobjgrp;
+
+	gk20a_dbg_info("");
+
+	/*check whether pmuboardobjgrp has a valid boardobj in index*/
+	if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)
+		return -EINVAL;
+
+	*ppboardobjpmudata = (struct nv_pmu_boardobj *)
+		&pgrp_set->objects[idx].data.board_obj;
+	gk20a_dbg_info(" Done");
+	return 0;
+}
+
+static u32 _clk_vf_points_pmustatus_instget(struct gk20a *g,
+					    void *pboardobjgrppmu,
+					    struct nv_pmu_boardobj_query **ppboardobjpmustatus,
+					    u8 idx)
+{
+	struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status *pgrp_get_status =
+		(struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status *)
+		pboardobjgrppmu;
+
+	/*check whether pmuboardobjgrp has a valid boardobj in index*/
+	if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)
+		return -EINVAL;
+
+	*ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
+			&pgrp_get_status->objects[idx].data.board_obj;
+	return 0;
+}
+
+u32 clk_vf_point_sw_setup(struct gk20a *g)
+{
+	u32 status;
+	struct boardobjgrp *pboardobjgrp = NULL;
+	struct clk_vf_points *pclkvfpointobjs;
+
+	gk20a_dbg_info("");
+
+	status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_vf_pointobjs.super);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+		"error creating boardobjgrp for clk vfpoint, status - 0x%x",
+		status);
+		goto done;
+	}
+
+	pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super;
+	pclkvfpointobjs = &(g->clk_pmu.clk_vf_pointobjs);
+
+	BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_VF_POINT);
+
+	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
+			clk, CLK, clk_vf_point, CLK_VF_POINT);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
+			status);
+		goto done;
+	}
+
+	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
+				&g->clk_pmu.clk_vf_pointobjs.super.super,
+				clk, CLK, clk_vf_point, CLK_VF_POINT);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
+			status);
+		goto done;
+	}
+
+	pboardobjgrp->pmudatainit = _clk_vf_points_pmudatainit;
+	pboardobjgrp->pmudatainstget  = _clk_vf_points_pmudata_instget;
+	pboardobjgrp->pmustatusinstget  = _clk_vf_points_pmustatus_instget;
+
+done:
+	gk20a_dbg_info(" done status %x", status);
+	return status;
+}
+
+u32 clk_vf_point_pmu_setup(struct gk20a *g)
+{
+	u32 status;
+	struct boardobjgrp *pboardobjgrp = NULL;
+
+	gk20a_dbg_info("");
+
+	pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super;
+
+	if (!pboardobjgrp->bconstructed)
+		return -EINVAL;
+
+	status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
+
+	gk20a_dbg_info("Done");
+	return status;
+}
+
+static u32 clk_vf_point_construct_super(struct gk20a *g,
+					struct boardobj **ppboardobj,
+					u16 size, void *pargs)
+{
+	struct clk_vf_point *pclkvfpoint;
+	struct clk_vf_point *ptmpvfpoint =
+			(struct clk_vf_point *)pargs;
+	u32 status = 0;
+
+	status = boardobj_construct_super(g, ppboardobj,
+		size, pargs);
+	if (status)
+		return -EINVAL;
+
+	pclkvfpoint = (struct clk_vf_point *)*ppboardobj;
+
+	pclkvfpoint->super.pmudatainit =
+			_clk_vf_point_pmudatainit_super;
+
+	pclkvfpoint->vfe_equ_idx = ptmpvfpoint->vfe_equ_idx;
+	pclkvfpoint->volt_rail_idx = ptmpvfpoint->volt_rail_idx;
+
+	return status;
+}
+
+static u32 _clk_vf_point_pmudatainit_volt(struct gk20a *g,
+					  struct boardobj *board_obj_ptr,
+					  struct nv_pmu_boardobj *ppmudata)
+{
+	u32 status = 0;
+	struct clk_vf_point_volt *pclk_vf_point_volt;
+	struct nv_pmu_clk_clk_vf_point_volt_boardobj_set *pset;
+
+	gk20a_dbg_info("");
+
+	status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata);
+	if (status != 0)
+		return status;
+
+	pclk_vf_point_volt =
+		(struct clk_vf_point_volt *)board_obj_ptr;
+
+	pset = (struct nv_pmu_clk_clk_vf_point_volt_boardobj_set *)
+		ppmudata;
+
+	pset->source_voltage_uv = pclk_vf_point_volt->source_voltage_uv;
+	pset->freq_delta_khz = pclk_vf_point_volt->freq_delta_khz;
+
+	return status;
+}
+
+static u32 _clk_vf_point_pmudatainit_freq(struct gk20a *g,
+					  struct boardobj *board_obj_ptr,
+					  struct nv_pmu_boardobj *ppmudata)
+{
+	u32 status = 0;
+	struct clk_vf_point_freq *pclk_vf_point_freq;
+	struct nv_pmu_clk_clk_vf_point_freq_boardobj_set *pset;
+
+	gk20a_dbg_info("");
+
+	status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata);
+	if (status != 0)
+		return status;
+
+	pclk_vf_point_freq =
+		(struct clk_vf_point_freq *)board_obj_ptr;
+
+	pset = (struct nv_pmu_clk_clk_vf_point_freq_boardobj_set *)
+		ppmudata;
+
+	pset->freq_mhz =
+		clkvfpointfreqmhzget(g, &pclk_vf_point_freq->super);
+
+	pset->volt_delta_uv = pclk_vf_point_freq->volt_delta_uv;
+
+	return status;
+}
+
+static u32 clk_vf_point_construct_volt(struct gk20a *g,
+				       struct boardobj **ppboardobj,
+				       u16 size, void *pargs)
+{
+	struct boardobj *ptmpobj = (struct boardobj *)pargs;
+	struct clk_vf_point_volt *pclkvfpoint;
+	struct clk_vf_point_volt *ptmpvfpoint =
+			(struct clk_vf_point_volt *)pargs;
+	u32 status = 0;
+
+	if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_VF_POINT_TYPE_VOLT)
+		return -EINVAL;
+
+	ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_VOLT);
+	status = clk_vf_point_construct_super(g, ppboardobj, size, pargs);
+	if (status)
+		return -EINVAL;
+
+	pclkvfpoint = (struct clk_vf_point_volt *)*ppboardobj;
+
+	pclkvfpoint->super.super.pmudatainit =
+			_clk_vf_point_pmudatainit_volt;
+
+	pclkvfpoint->source_voltage_uv = ptmpvfpoint->source_voltage_uv;
+
+	return status;
+}
+
+static u32 clk_vf_point_construct_freq(struct gk20a *g,
+				       struct boardobj **ppboardobj,
+				       u16 size, void *pargs)
+{
+	struct boardobj *ptmpobj = (struct boardobj *)pargs;
+	struct clk_vf_point_freq *pclkvfpoint;
+	struct clk_vf_point_freq *ptmpvfpoint =
+			(struct clk_vf_point_freq *)pargs;
+	u32 status = 0;
+
+	if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_VF_POINT_TYPE_FREQ)
+		return -EINVAL;
+
+	ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_FREQ);
+	status = clk_vf_point_construct_super(g, ppboardobj, size, pargs);
+	if (status)
+		return -EINVAL;
+
+	pclkvfpoint = (struct clk_vf_point_freq *)*ppboardobj;
+
+	pclkvfpoint->super.super.pmudatainit =
+			_clk_vf_point_pmudatainit_freq;
+
+	clkvfpointfreqmhzset(g, &pclkvfpoint->super,
+		clkvfpointfreqmhzget(g, &ptmpvfpoint->super));
+
+	return status;
+}
+
+struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs)
+{
+	struct boardobj *board_obj_ptr = NULL;
+	u32 status;
+
+	gk20a_dbg_info("");
+	switch (BOARDOBJ_GET_TYPE(pargs)) {
+	case CTRL_CLK_CLK_VF_POINT_TYPE_FREQ:
+		status = clk_vf_point_construct_freq(g, &board_obj_ptr,
+			sizeof(struct clk_vf_point_freq), pargs);
+		break;
+
+	case CTRL_CLK_CLK_VF_POINT_TYPE_VOLT:
+		status = clk_vf_point_construct_volt(g, &board_obj_ptr,
+			sizeof(struct clk_vf_point_volt), pargs);
+		break;
+
+	default:
+		return NULL;
+	}
+
+	if (status)
+		return NULL;
+
+	gk20a_dbg_info(" Done");
+
+	return (struct clk_vf_point *)board_obj_ptr;
+}
+
+static u32 _clk_vf_point_pmudatainit_super(struct gk20a *g,
+					   struct boardobj *board_obj_ptr,
+					   struct nv_pmu_boardobj *ppmudata)
+{
+	u32 status = 0;
+	struct clk_vf_point *pclk_vf_point;
+	struct nv_pmu_clk_clk_vf_point_boardobj_set *pset;
+
+	gk20a_dbg_info("");
+
+	status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
+	if (status != 0)
+		return status;
+
+	pclk_vf_point =
+		(struct clk_vf_point *)board_obj_ptr;
+
+	pset = (struct nv_pmu_clk_clk_vf_point_boardobj_set *)
+		ppmudata;
+
+
+	pset->vfe_equ_idx = pclk_vf_point->vfe_equ_idx;
+	pset->volt_rail_idx = pclk_vf_point->volt_rail_idx;
+	return status;
+}
+
+
+static u32 clk_vf_point_update(struct gk20a *g,
+				struct boardobj *board_obj_ptr,
+				struct nv_pmu_boardobj *ppmudata)
+{
+	struct clk_vf_point *pclk_vf_point;
+	struct nv_pmu_clk_clk_vf_point_boardobj_get_status *pstatus;
+
+	gk20a_dbg_info("");
+
+
+	pclk_vf_point =
+		(struct clk_vf_point *)board_obj_ptr;
+
+	pstatus = (struct nv_pmu_clk_clk_vf_point_boardobj_get_status *)
+		ppmudata;
+
+	if (pstatus->super.type != pclk_vf_point->super.type) {
+		gk20a_err(dev_from_gk20a(g),
+			"pmu data and boardobj type not matching");
+		return -EINVAL;
+	}
+	/* now copy VF pair */
+	memcpy(&pclk_vf_point->pair, &pstatus->pair,
+		sizeof(struct ctrl_clk_vf_pair));
+	return 0;
+}
+
+/*get latest vf point data from PMU */
+u32 clk_vf_point_cache(struct gk20a *g)
+{
+
+	struct clk_vf_points *pclk_vf_points;
+	struct boardobjgrp *pboardobjgrp;
+	struct boardobjgrpmask *pboardobjgrpmask;
+	struct nv_pmu_boardobjgrp_super *pboardobjgrppmu;
+	struct boardobj *pboardobj = NULL;
+	struct nv_pmu_boardobj_query *pboardobjpmustatus = NULL;
+	u32 status;
+	u8 index;
+
+	gk20a_dbg_info("");
+	pclk_vf_points = &g->clk_pmu.clk_vf_pointobjs;
+	pboardobjgrp = &pclk_vf_points->super.super;
+	pboardobjgrpmask = &pclk_vf_points->super.mask.super;
+
+	status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g), "err getting boardobjs from pmu");
+		return status;
+	}
+	pboardobjgrppmu = pboardobjgrp->pmu.getstatus.buf;
+
+	BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
+		status = pboardobjgrp->pmustatusinstget(g,
+				(struct nv_pmu_boardobjgrp *)pboardobjgrppmu,
+				&pboardobjpmustatus, index);
+		if (status) {
+			gk20a_err(dev_from_gk20a(g),
+				"could not get status object instance");
+			return status;
+		}
+
+		status = clk_vf_point_update(g, pboardobj,
+			(struct nv_pmu_boardobj *)pboardobjpmustatus);
+		if (status) {
+			gk20a_err(dev_from_gk20a(g),
+				"invalid data from pmu at %d", index);
+			return status;
+		}
+	}
+
+	return 0;
+}

drivers/gpu/nvgpu/clk/clk_vf_point.h

@@ -0,0 +1,74 @@
+/*
+* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*/
+
+#ifndef _CLKVFPOINT_H_
+#define _CLKVFPOINT_H_
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "boardobj/boardobjgrpmask.h"
+
+u32 clk_vf_point_sw_setup(struct gk20a *g);
+u32 clk_vf_point_pmu_setup(struct gk20a *g);
+u32 clk_vf_point_cache(struct gk20a *g);
+
+struct clk_vf_points {
+	struct boardobjgrp_e255 super;
+};
+
+struct clk_vf_point {
+	struct boardobj super;
+	u8  vfe_equ_idx;
+	u8  volt_rail_idx;
+	struct ctrl_clk_vf_pair pair;
+};
+
+struct clk_vf_point_volt {
+	struct clk_vf_point super;
+	u32 source_voltage_uv;
+	int freq_delta_khz;
+};
+
+struct clk_vf_point_freq {
+	struct clk_vf_point super;
+	int volt_delta_uv;
+};
+
+#define CLK_CLK_VF_POINT_GET(pclk, idx)                                        \
+	((struct clk_vf_point *)BOARDOBJGRP_OBJ_GET_BY_IDX(                    \
+		&pclk->clk_vf_pointobjs.super.super, (u8)(idx)))
+
+#define clkvfpointpairget(pvfpoint)                                            \
+	(&((pvfpoint)->pair))
+
+#define clkvfpointfreqmhzget(pgpu, pvfpoint)                                   \
+	CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(clkvfpointpairget(pvfpoint))
+
+#define clkvfpointfreqdeltamhzGet(pgpu, pvfPoint)                              \
+	((BOARDOBJ_GET_TYPE(pvfpoint) == CTRL_CLK_CLK_VF_POINT_TYPE_VOLT) ?    \
+	(((struct clk_vf_point_volt *)(pvfpoint))->freq_delta_khz / 1000) : 0)
+
+#define clkvfpointfreqmhzset(pgpu, pvfpoint, _freqmhz)                         \
+	CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(clkvfpointpairget(pvfpoint), _freqmhz)
+
+#define clkvfpointvoltageuvset(pgpu, pvfpoint, _voltageuv)                     \
+	CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(clkvfpointpairget(pvfpoint),           \
+	_voltageuv)
+
+#define clkvfpointvoltageuvget(pgpu, pvfpoint)                          \
+	CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(clkvfpointpairget(pvfpoint))	\
+
+struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs);
+
+#endif

drivers/gpu/nvgpu/clk/clk_vin.c

@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "clk.h"
+#include "clk_vin.h"
+#include "include/bios.h"
+#include "boardobj/boardobjgrp.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "pmuif/gpmuifboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "gm206/bios_gm206.h"
+#include "ctrl/ctrlvolt.h"
+#include "gk20a/pmu_gk20a.h"
+#include "gp106/hw_fuse_gp106.h"
+
+static u32 devinit_get_vin_device_table(struct gk20a *g,
+		struct avfsvinobjs *pvinobjs);
+
+static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs);
+
+static u32 vin_device_init_pmudata_super(struct gk20a *g,
+				  struct boardobj *board_obj_ptr,
+				  struct nv_pmu_boardobj *ppmudata);
+
+static u32 read_vin_cal_fuse_rev(struct gk20a *g)
+{
+	return fuse_vin_cal_fuse_rev_v(
+		gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
+}
+
+static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
+					     u32 vin_id, u32 *slope,
+					     u32 *intercept)
+{
+	u32 data = 0;
+	u32 interceptdata = 0;
+	u32 slopedata = 0;
+	u32 gpc0data;
+	u32 gpc0slopedata;
+	u32 gpc0interceptdata;
+
+	/* read gpc0 irrespective of vin id */
+	gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
+	if (gpc0data == 0xFFFFFFFF)
+		return -EINVAL;
+
+	switch (vin_id) {
+	case CTRL_CLK_VIN_ID_GPC0:
+		break;
+
+	case CTRL_CLK_VIN_ID_GPC1:
+		data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
+		break;
+
+	case CTRL_CLK_VIN_ID_GPC2:
+		data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
+		break;
+
+	case CTRL_CLK_VIN_ID_GPC3:
+		data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
+		break;
+
+	case CTRL_CLK_VIN_ID_GPC4:
+		data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
+		break;
+
+	case CTRL_CLK_VIN_ID_GPC5:
+		data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
+		break;
+
+	case CTRL_CLK_VIN_ID_SYS:
+	case CTRL_CLK_VIN_ID_XBAR:
+	case CTRL_CLK_VIN_ID_LTC:
+		data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
+		break;
+
+	case CTRL_CLK_VIN_ID_SRAM:
+		data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
+		break;
+
+	default:
+		return -EINVAL;
+	}
+	if (data == 0xFFFFFFFF)
+		return -EINVAL;
+
+	gpc0interceptdata = fuse_vin_cal_gpc0_icpt_data_v(gpc0data) * 1000;
+	gpc0interceptdata = gpc0interceptdata >>
+		fuse_vin_cal_gpc0_icpt_frac_size_v();
+
+	switch (vin_id) {
+	case CTRL_CLK_VIN_ID_GPC0:
+		break;
+
+	case CTRL_CLK_VIN_ID_GPC1:
+	case CTRL_CLK_VIN_ID_GPC2:
+	case CTRL_CLK_VIN_ID_GPC3:
+	case CTRL_CLK_VIN_ID_GPC4:
+	case CTRL_CLK_VIN_ID_GPC5:
+	case CTRL_CLK_VIN_ID_SYS:
+	case CTRL_CLK_VIN_ID_XBAR:
+	case CTRL_CLK_VIN_ID_LTC:
+		interceptdata =
+			(fuse_vin_cal_gpc1_icpt_data_v(data)) * 1000;
+		interceptdata = interceptdata >>
+			fuse_vin_cal_gpc1_icpt_frac_size_v();
+		break;
+
+	case CTRL_CLK_VIN_ID_SRAM:
+		interceptdata =
+			(fuse_vin_cal_sram_icpt_data_v(data)) * 1000;
+		interceptdata = interceptdata >>
+			fuse_vin_cal_sram_icpt_frac_size_v();
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	if (data & fuse_vin_cal_gpc1_icpt_sign_f())
+		*intercept = gpc0interceptdata - interceptdata;
+	else
+		*intercept = gpc0interceptdata + interceptdata;
+
+	/* slope */
+	gpc0slopedata = (fuse_vin_cal_gpc0_slope_data_v(gpc0data)) * 1000;
+	gpc0slopedata = gpc0slopedata >>
+		fuse_vin_cal_gpc0_slope_frac_size_v();
+
+	switch (vin_id) {
+	case CTRL_CLK_VIN_ID_GPC0:
+		break;
+
+	case CTRL_CLK_VIN_ID_GPC1:
+	case CTRL_CLK_VIN_ID_GPC2:
+	case CTRL_CLK_VIN_ID_GPC3:
+	case CTRL_CLK_VIN_ID_GPC4:
+	case CTRL_CLK_VIN_ID_GPC5:
+	case CTRL_CLK_VIN_ID_SYS:
+	case CTRL_CLK_VIN_ID_XBAR:
+	case CTRL_CLK_VIN_ID_LTC:
+	case CTRL_CLK_VIN_ID_SRAM:
+		slopedata =
+			(fuse_vin_cal_gpc1_slope_data_v(data)) * 1000;
+		slopedata = slopedata >>
+			fuse_vin_cal_gpc1_slope_frac_size_v();
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	if (data & fuse_vin_cal_gpc1_slope_sign_f())
+		*slope = gpc0slopedata - slopedata;
+	else
+		*slope = gpc0slopedata + slopedata;
+	return 0;
+}
+
+static u32 _clk_vin_devgrp_pmudatainit_super(struct gk20a *g,
+					     struct boardobjgrp *pboardobjgrp,
+					     struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
+{
+	struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header *pset =
+		(struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header *)
+		pboardobjgrppmu;
+	struct avfsvinobjs *pvin_obbj = (struct avfsvinobjs *)pboardobjgrp;
+	u32 status = 0;
+
+	gk20a_dbg_info("");
+
+	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
+
+	pset->b_vin_is_disable_allowed = pvin_obbj->vin_is_disable_allowed;
+
+	gk20a_dbg_info(" Done");
+	return status;
+}
+
+static u32 _clk_vin_devgrp_pmudata_instget(struct gk20a *g,
+					   struct nv_pmu_boardobjgrp *pmuboardobjgrp,
+					   struct nv_pmu_boardobj **ppboardobjpmudata,
+					   u8 idx)
+{
+	struct nv_pmu_clk_clk_vin_device_boardobj_grp_set *pgrp_set =
+		(struct nv_pmu_clk_clk_vin_device_boardobj_grp_set *)
+		pmuboardobjgrp;
+
+	gk20a_dbg_info("");
+
+	/*check whether pmuboardobjgrp has a valid boardobj in index*/
+	if (((u32)BIT(idx) &
+		pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
+		return -EINVAL;
+
+	*ppboardobjpmudata = (struct nv_pmu_boardobj *)
+		&pgrp_set->objects[idx].data.board_obj;
+	gk20a_dbg_info(" Done");
+	return 0;
+}
+
+static u32 _clk_vin_devgrp_pmustatus_instget(struct gk20a *g,
+					     void *pboardobjgrppmu,
+					     struct nv_pmu_boardobj_query **ppboardobjpmustatus,
+					     u8 idx)
+{
+	struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status *pgrp_get_status =
+		(struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status *)
+		pboardobjgrppmu;
+
+	/*check whether pmuboardobjgrp has a valid boardobj in index*/
+	if (((u32)BIT(idx) &
+		pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
+		return -EINVAL;
+
+	*ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
+			&pgrp_get_status->objects[idx].data.board_obj;
+	return 0;
+}
+
+u32 clk_vin_sw_setup(struct gk20a *g)
+{
+	u32 status;
+	struct boardobjgrp *pboardobjgrp = NULL;
+	u32 slope;
+	u32 intercept;
+	struct vin_device *pvindev;
+	struct avfsvinobjs *pvinobjs;
+	u8 i;
+
+	gk20a_dbg_info("");
+
+	status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_vinobjs.super);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"error creating boardobjgrp for clk vin, statu - 0x%x",
+			status);
+		goto done;
+	}
+
+	pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super;
+	pvinobjs = &g->clk_pmu.avfs_vinobjs;
+
+	BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, VIN_DEVICE);
+
+	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
+			clk, CLK, clk_vin_device, CLK_VIN_DEVICE);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
+			status);
+		goto done;
+	}
+
+	pboardobjgrp->pmudatainit  = _clk_vin_devgrp_pmudatainit_super;
+	pboardobjgrp->pmudatainstget  = _clk_vin_devgrp_pmudata_instget;
+	pboardobjgrp->pmustatusinstget  = _clk_vin_devgrp_pmustatus_instget;
+
+	status = devinit_get_vin_device_table(g, &g->clk_pmu.avfs_vinobjs);
+	if (status)
+		goto done;
+
+	/*update vin calibration to fuse */
+	if (pvinobjs->calibration_rev_vbios == read_vin_cal_fuse_rev(g)) {
+		BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
+				     struct vin_device *, pvindev, i) {
+			slope = 0;
+			intercept = 0;
+			pvindev = CLK_GET_VIN_DEVICE(pvinobjs, i);
+			status = read_vin_cal_slope_intercept_fuse(g,
+					pvindev->id, &slope, &intercept);
+			if (status) {
+				gk20a_err(dev_from_gk20a(g),
+				"err reading vin cal for id %x", pvindev->id);
+				goto done;
+			}
+			if (slope != 0 && intercept != 0) {
+				pvindev->slope = slope;
+				pvindev->intercept = intercept;
+			}
+		}
+	}
+	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
+				&g->clk_pmu.avfs_vinobjs.super.super,
+				clk, CLK, clk_vin_device, CLK_VIN_DEVICE);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g),
+			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
+			status);
+		goto done;
+	}
+
+done:
+	gk20a_dbg_info(" done status %x", status);
+	return status;
+}
+
+u32 clk_vin_pmu_setup(struct gk20a *g)
+{
+	u32 status;
+	struct boardobjgrp *pboardobjgrp = NULL;
+
+	gk20a_dbg_info("");
+
+	pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super;
+
+	if (!pboardobjgrp->bconstructed)
+		return -EINVAL;
+
+	status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
+
+	gk20a_dbg_info("Done");
+	return status;
+}
+
+static u32 devinit_get_vin_device_table(struct gk20a *g,
+		struct avfsvinobjs *pvinobjs)
+{
+	u32 status = 0;
+	u8 *vin_table_ptr = NULL;
+	struct vin_descriptor_header_10 vin_desc_table_header = { 0 };
+	struct vin_descriptor_entry_10 vin_desc_table_entry = { 0 };
+	u8 *vin_tbl_entry_ptr = NULL;
+	u32 index = 0;
+	u32 slope, intercept;
+	struct vin_device vin_dev_data;
+	struct vin_device *pvin_dev;
+
+	gk20a_dbg_info("");
+
+	if (g->ops.bios.get_perf_table_ptrs) {
+		vin_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
+				g->bios.clock_token, VIN_TABLE);
+		if (vin_table_ptr == NULL) {
+			status = -1;
+			goto done;
+		}
+	}
+
+	memcpy(&vin_desc_table_header, vin_table_ptr,
+	       sizeof(struct vin_descriptor_header_10));
+
+	pvinobjs->calibration_rev_vbios =
+			BIOS_GET_FIELD(vin_desc_table_header.flags0,
+				NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION);
+	pvinobjs->vin_is_disable_allowed =
+			BIOS_GET_FIELD(vin_desc_table_header.flags0,
+				NV_VIN_DESC_FLAGS0_DISABLE_CONTROL);
+
+	/* VIN calibration slope: XX.YYY mV/code => XXYYY uV/code*/
+	slope = ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal,
+			NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER) * 1000)) +
+		((BIOS_GET_FIELD(vin_desc_table_header.vin_cal,
+			NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION)));
+
+	/* VIN calibration intercept: ZZZ.W mV => ZZZW00 uV */
+	intercept = ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal,
+			NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER) * 1000)) +
+		    ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal,
+			NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION) * 100));
+
+	/* Read table entries*/
+	vin_tbl_entry_ptr = vin_table_ptr + vin_desc_table_header.header_sizee;
+	for (index = 0; index < vin_desc_table_header.entry_count; index++) {
+		u32 vin_id;
+
+		memcpy(&vin_desc_table_entry, vin_tbl_entry_ptr,
+		       sizeof(struct vin_descriptor_entry_10));
+
+		if (vin_desc_table_entry.vin_device_type == CTRL_CLK_VIN_TYPE_DISABLED)
+			continue;
+
+		vin_id = vin_desc_table_entry.vin_device_id;
+
+		vin_dev_data.super.type =
+			(u8)vin_desc_table_entry.vin_device_type;
+		vin_dev_data.id = (u8)vin_desc_table_entry.vin_device_id;
+		vin_dev_data.volt_domain_vbios =
+			(u8)vin_desc_table_entry.volt_domain_vbios;
+		vin_dev_data.slope = slope;
+		vin_dev_data.intercept = intercept;
+
+		vin_dev_data.flls_shared_mask = 0;
+
+		pvin_dev = construct_vin_device(g, (void *)&vin_dev_data);
+
+		status = boardobjgrp_objinsert(&pvinobjs->super.super,
+				(struct boardobj *)pvin_dev, index);
+
+		vin_tbl_entry_ptr += vin_desc_table_header.entry_size;
+	}
+
+done:
+	gk20a_dbg_info(" done status %x", status);
+	return status;
+}
+
+static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs)
+{
+	struct boardobj *board_obj_ptr = NULL;
+	struct vin_device *pvin_dev;
+	struct vin_device *board_obj_vin_ptr = NULL;
+	u32 status;
+
+	gk20a_dbg_info("");
+	status = boardobj_construct_super(g, &board_obj_ptr,
+		sizeof(struct vin_device), pargs);
+	if (status)
+		return NULL;
+
+	/*got vin board obj allocated now fill it into boardobj grp*/
+	pvin_dev = (struct vin_device *)pargs;
+	board_obj_vin_ptr = (struct vin_device *)board_obj_ptr;
+	/* override super class interface */
+	board_obj_ptr->pmudatainit = vin_device_init_pmudata_super;
+	board_obj_vin_ptr->id = pvin_dev->id;
+	board_obj_vin_ptr->volt_domain_vbios = pvin_dev->volt_domain_vbios;
+	board_obj_vin_ptr->slope = pvin_dev->slope;
+	board_obj_vin_ptr->intercept = pvin_dev->intercept;
+	board_obj_vin_ptr->flls_shared_mask = pvin_dev->flls_shared_mask;
+	board_obj_vin_ptr->volt_domain = CTRL_VOLT_DOMAIN_LOGIC;
+
+	gk20a_dbg_info(" Done");
+
+	return (struct vin_device *)board_obj_ptr;
+}
+
+static u32 vin_device_init_pmudata_super(struct gk20a *g,
+					 struct boardobj *board_obj_ptr,
+					 struct nv_pmu_boardobj *ppmudata)
+{
+	u32 status = 0;
+	struct vin_device *pvin_dev;
+	struct nv_pmu_clk_clk_vin_device_boardobj_set *perf_pmu_data;
+
+	gk20a_dbg_info("");
+
+	status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
+	if (status != 0)
+		return status;
+
+	pvin_dev = (struct vin_device *)board_obj_ptr;
+	perf_pmu_data = (struct nv_pmu_clk_clk_vin_device_boardobj_set *)
+		ppmudata;
+
+	perf_pmu_data->id = pvin_dev->id;
+	perf_pmu_data->intercept = pvin_dev->intercept;
+	perf_pmu_data->volt_domain = pvin_dev->volt_domain;
+	perf_pmu_data->slope = pvin_dev->slope;
+	perf_pmu_data->flls_shared_mask = pvin_dev->flls_shared_mask;
+
+	gk20a_dbg_info(" Done");
+
+	return status;
+}

drivers/gpu/nvgpu/clk/clk_vin.h

@@ -0,0 +1,56 @@
+/*
+* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*/
+
+#ifndef _CLKVIN_H_
+#define _CLKVIN_H_
+
+#include "boardobj/boardobj.h"
+#include "boardobj/boardobjgrp.h"
+#include "clk.h"
+
+struct vin_device;
+struct clk_pmupstate;
+
+struct avfsvinobjs {
+	struct boardobjgrp_e32 super;
+	u8 calibration_rev_vbios;
+	u8 calibration_rev_fused;
+	bool vin_is_disable_allowed;
+};
+typedef u32 vin_device_state_load(struct gk20a *g,
+			struct clk_pmupstate *clk, struct vin_device *pdev);
+
+struct vin_device {
+	struct boardobj super;
+	u8 id;
+	u8 volt_domain;
+	u8 volt_domain_vbios;
+	u32 slope;
+	u32 intercept;
+	u32 flls_shared_mask;
+
+	vin_device_state_load  *state_load;
+};
+
+/* get vin device object from descriptor table index*/
+#define CLK_GET_VIN_DEVICE(pvinobjs, dev_index)                               \
+	((struct vin_device *)BOARDOBJGRP_OBJ_GET_BY_IDX(                       \
+	((struct boardobjgrp *)&(pvinobjs->super.super)), (dev_index)))
+
+boardobj_construct construct_vindevice;
+boardobj_pmudatainit vindeviceinit_pmudata_super;
+
+u32 clk_vin_sw_setup(struct gk20a *g);
+u32 clk_vin_pmu_setup(struct gk20a *g);
+
+#endif

drivers/gpu/nvgpu/gp106/acr_gp106.h

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __ACR_GP106_H_
+#define __ACR_GP106_H_
+
+#include "gm20b/acr_gm20b.h"
+#include "gm206/acr_gm206.h"
+
+#define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin"
+#define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin"
+#define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin"
+#define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin"
+
+struct lsf_ucode_desc_v1 {
+	u8  prd_keys[2][16];
+	u8  dbg_keys[2][16];
+	u32 b_prd_present;
+	u32 b_dbg_present;
+	u32 falcon_id;
+	u32 bsupports_versioning;
+	u32 version;
+	u32 dep_map_count;
+	u8  dep_map[LSF_FALCON_ID_END * 2 * 4];
+	u8  kdf[16];
+};
+
+struct lsf_wpr_header_v1 {
+	u32  falcon_id;
+	u32  lsb_offset;
+	u32  bootstrap_owner;
+	u32  lazy_bootstrap;
+	u32  bin_version;
+	u32  status;
+};
+
+struct lsf_lsb_header_v1 {
+	struct lsf_ucode_desc_v1 signature;
+	u32 ucode_off;
+	u32 ucode_size;
+	u32 data_size;
+	u32 bl_code_size;
+	u32 bl_imem_off;
+	u32 bl_data_off;
+	u32 bl_data_size;
+	u32 app_code_off;
+	u32 app_code_size;
+	u32 app_data_off;
+	u32 app_data_size;
+	u32 flags;
+};
+
+struct flcn_ucode_img_v1 {
+	u32 *header; /*only some falcons have header*/
+	u32 *data;
+	struct pmu_ucode_desc_v1 *desc;  /*only some falcons have descriptor*/
+	u32 data_size;
+	void *fw_ver; /*NV2080_CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct*/
+	u8 load_entire_os_data; /* load the whole osData section at boot time.*/
+	struct lsf_ucode_desc_v1 *lsf_desc; /* NULL if not a light secure falcon.*/
+	u8 free_res_allocs;/*True if there a resources to freed by the client.*/
+	u32 flcn_inst;
+};
+
+struct lsfm_managed_ucode_img_v2 {
+	struct lsfm_managed_ucode_img_v2 *next;
+	struct lsf_wpr_header_v1 wpr_header;
+	struct lsf_lsb_header_v1 lsb_header;
+	union flcn_bl_generic_desc_v1 bl_gen_desc;
+	u32 bl_gen_desc_size;
+	u32 full_ucode_size;
+	struct flcn_ucode_img_v1 ucode_img;
+};
+struct ls_flcn_mgr_v1 {
+	u16 managed_flcn_cnt;
+	u32 wpr_size;
+	u32 disable_mask;
+	struct lsfm_managed_ucode_img_v2 *ucode_img_list;
+	void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
+};
+
+struct flcn_acr_region_prop_v1 {
+	u32   start_addr;
+	u32   end_addr;
+	u32   region_id;
+	u32   read_mask;
+	u32   write_mask;
+	u32   client_mask;
+	u32   shadowmMem_startaddress;
+};
+
+/*!
+ * no_regions   - Number of regions used.
+ * region_props   - Region properties
+ */
+struct flcn_acr_regions_v1 {
+	u32                     no_regions;
+	struct flcn_acr_region_prop_v1   region_props[T210_FLCN_ACR_MAX_REGIONS];
+};
+
+struct flcn_acr_desc_v1 {
+	union {
+		u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
+	} ucode_reserved_space;
+	u32 signatures[4];
+	/*Always 1st*/
+	u32 wpr_region_id;
+	u32 wpr_offset;
+	u32 mmu_mem_range;
+	struct flcn_acr_regions_v1 regions;
+	u32 nonwpr_ucode_blob_size;
+	u64 nonwpr_ucode_blob_start;
+	u32 dummy[4];  //ACR_BSI_VPR_DESC
+};
+
+void gp106_init_secure_pmu(struct gpu_ops *gops);
+
+#endif /*__PMU_GP106_H_*/

drivers/gpu/nvgpu/gp106/bios_gp106.c

@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gm206/bios_gm206.h"
+#include "bios_gp106.h"
+#include "hw_gc6_gp106.h"
+
+static void gp106_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition,
+	u32 reg, u32 stride, u32 count, u32 data_table_offset)
+{
+	u8 i;
+	u32 data, strap, index;
+
+	if (*condition) {
+
+		strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
+
+		index = g->bios.mem_strap_xlat_tbl_ptr ?
+			gm206_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
+				strap) : strap;
+
+		for (i = 0; i < count; i++) {
+			data = gm206_bios_read_u32(g, data_table_offset + ((i *
+				g->bios.mem_strap_data_count + index) *
+				sizeof(u32)));
+			gk20a_writel(g, reg, data);
+			reg += stride;
+		}
+	}
+}
+
+static void gp106_init_condition(struct gk20a *g, bool *condition,
+	u32 condition_id)
+{
+	struct condition_entry entry;
+
+	entry.cond_addr = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
+		sizeof(entry)*condition_id);
+	entry.cond_mask = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
+		sizeof(entry)*condition_id + 4);
+	entry.cond_compare = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
+		sizeof(entry)*condition_id + 8);
+
+	if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
+		!= entry.cond_compare) {
+		*condition = false;
+	}
+}
+
+static int gp106_execute_script(struct gk20a *g, u32 offset)
+{
+	u8 opcode;
+	u32 ip;
+	u32 operand[8];
+	bool condition, end;
+	int status = 0;
+
+	ip = offset;
+	condition = true;
+	end = false;
+
+	while (!end) {
+
+		opcode = gm206_bios_read_u8(g, ip++);
+
+		switch (opcode) {
+
+		case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
+			operand[0] = gm206_bios_read_u32(g, ip);
+			operand[1] = gm206_bios_read_u8(g, ip+4);
+			operand[2] = gm206_bios_read_u8(g, ip+5);
+			ip += 6;
+
+			gp106_init_xmemsel_zm_nv_reg_array(g, &condition,
+				operand[0], operand[1], operand[2], ip);
+			ip += operand[2] * sizeof(u32) *
+				g->bios.mem_strap_data_count;
+			break;
+
+		case INIT_CONDITION:
+			operand[0] = gm206_bios_read_u8(g, ip);
+			ip++;
+
+			gp106_init_condition(g, &condition, operand[0]);
+			break;
+
+		case INIT_RESUME:
+			condition = true;
+			break;
+
+		case INIT_DONE:
+			end = true;
+			break;
+
+		default:
+			gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode);
+			end = true;
+			status = -EINVAL;
+			break;
+		}
+	}
+
+	return status;
+}
+
+void gp106_init_bios(struct gpu_ops *gops)
+{
+	gm206_init_bios(gops);
+	gops->bios.execute_script = gp106_execute_script;
+}

drivers/gpu/nvgpu/gp106/bios_gp106.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef NVGPU_BIOS_GP106_H
+#define NVGPU_BIOS_GP106_H
+
+struct gpu_ops;
+
+#define INIT_DONE 0x71
+#define INIT_RESUME 0x72
+#define INIT_CONDITION 0x75
+#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f
+
+struct condition_entry {
+	u32 cond_addr;
+	u32 cond_mask;
+	u32 cond_compare;
+} __packed;
+
+void gp106_init_bios(struct gpu_ops *gops);
+#endif

drivers/gpu/nvgpu/gp106/clk_arb_gp106.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+
+#include "clk/clk_arb.h"
+#include "clk_arb_gp106.h"
+
+static u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
+{
+	(void)g;
+	return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK);
+}
+
+static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+		u16 *min_mhz, u16 *max_mhz)
+{
+	enum nv_pmu_clk_clkwhich clkwhich;
+	struct clk_set_info *p0_info;
+	struct clk_set_info *p5_info;
+	struct avfsfllobjs *pfllobjs =  &(g->clk_pmu.avfs_fllobjs);
+
+	u16 limit_min_mhz;
+
+	switch (api_domain) {
+	case CTRL_CLK_DOMAIN_MCLK:
+		clkwhich = clkwhich_mclk;
+		break;
+
+	case CTRL_CLK_DOMAIN_GPC2CLK:
+		clkwhich = clkwhich_gpc2clk;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	p5_info = pstate_get_clk_set_info(g,
+			CTRL_PERF_PSTATE_P5, clkwhich);
+	if (!p5_info)
+		return -EINVAL;
+
+	p0_info = pstate_get_clk_set_info(g,
+			CTRL_PERF_PSTATE_P0, clkwhich);
+	if (!p0_info)
+		return -EINVAL;
+
+	limit_min_mhz = p5_info->min_mhz;
+	/* WAR for DVCO min */
+	if (api_domain == CTRL_CLK_DOMAIN_GPC2CLK)
+		if ((pfllobjs->max_min_freq_mhz) &&
+		(pfllobjs->max_min_freq_mhz > limit_min_mhz))
+			limit_min_mhz = pfllobjs->max_min_freq_mhz;
+
+	*min_mhz = limit_min_mhz;
+	*max_mhz = p0_info->max_mhz;
+
+	return 0;
+}
+
+static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
+		u16 *default_mhz)
+{
+	enum nv_pmu_clk_clkwhich clkwhich;
+	struct clk_set_info *p0_info;
+
+	switch (api_domain) {
+	case CTRL_CLK_DOMAIN_MCLK:
+		clkwhich = clkwhich_mclk;
+		break;
+
+	case CTRL_CLK_DOMAIN_GPC2CLK:
+		clkwhich = clkwhich_gpc2clk;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	p0_info = pstate_get_clk_set_info(g,
+			CTRL_PERF_PSTATE_P0, clkwhich);
+	if (!p0_info)
+		return -EINVAL;
+
+	*default_mhz = p0_info->max_mhz;
+
+	return 0;
+}
+
+void gp106_init_clk_arb_ops(struct gpu_ops *gops)
+{
+	gops->clk_arb.get_arbiter_clk_domains = gp106_get_arbiter_clk_domains;
+	gops->clk_arb.get_arbiter_clk_range = gp106_get_arbiter_clk_range;
+	gops->clk_arb.get_arbiter_clk_default = gp106_get_arbiter_clk_default;
+}

drivers/gpu/nvgpu/gp106/clk_arb_gp106.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef CLK_ARB_GP106_H
+#define CLK_ARB_GP106_H
+
+void gp106_init_clk_arb_ops(struct gpu_ops *gops);
+
+#endif /* CLK_ARB_GP106_H */

drivers/gpu/nvgpu/gp106/clk_gp106.c

@@ -0,0 +1,273 @@
+/*
+ * GP106 Clocks
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>	/* for mdelay */
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/clk/tegra.h>
+#include <linux/tegra-fuse.h>
+
+#include "gk20a/gk20a.h"
+#include "hw_trim_gp106.h"
+#include "clk_gp106.h"
+#include "clk/clk_arb.h"
+
+#define gk20a_dbg_clk(fmt, arg...) \
+	gk20a_dbg(gpu_dbg_clk, fmt, ##arg)
+
+#ifdef CONFIG_DEBUG_FS
+static int clk_gp106_debugfs_init(struct gk20a *g);
+#endif
+
+#define NUM_NAMEMAPS	4
+#define XTAL4X_KHZ 108000
+
+
+static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *);
+static u16 gp106_clk_get_rate(struct gk20a *g, u32 api_domain);
+static u32 gp106_crystal_clk_hz(struct gk20a *g)
+{
+	return (XTAL4X_KHZ * 1000);
+}
+
+static u16 gp106_clk_get_rate(struct gk20a *g, u32 api_domain)
+{
+	struct clk_gk20a *clk = &g->clk;
+	u32 freq_khz;
+	u32 i;
+	struct namemap_cfg *c = NULL;
+
+	for (i = 0; i < clk->namemap_num; i++) {
+		if (api_domain == clk->namemap_xlat_table[i]) {
+			c = &clk->clk_namemap[i];
+			break;
+		}
+	}
+
+	if (!c)
+		return 0;
+
+	freq_khz = c->is_counter ? c->scale * gp106_get_rate_cntr(g, c) :
+		0; /* TODO: PLL read */
+
+	/* Convert to MHZ */
+	return (u16) (freq_khz/1000);
+}
+
+static int gp106_init_clk_support(struct gk20a *g) {
+	struct clk_gk20a *clk = &g->clk;
+	u32 err = 0;
+
+	gk20a_dbg_fn("");
+
+	mutex_init(&clk->clk_mutex);
+
+	clk->clk_namemap = (struct namemap_cfg *)
+		kzalloc(sizeof(struct namemap_cfg) * NUM_NAMEMAPS, GFP_KERNEL);
+
+	if (!clk->clk_namemap)
+		return -ENOMEM;
+
+	clk->namemap_xlat_table = kcalloc(NUM_NAMEMAPS, sizeof(u32),
+		GFP_KERNEL);
+
+	if (!clk->namemap_xlat_table) {
+		kfree(clk->clk_namemap);
+		return -ENOMEM;
+	}
+
+	clk->clk_namemap[0] = (struct namemap_cfg) {
+		.namemap = CLK_NAMEMAP_INDEX_GPC2CLK,
+		.is_enable = 1,
+		.is_counter = 1,
+		.g = g,
+		.cntr.reg_ctrl_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(),
+		.cntr.reg_ctrl_idx  =
+			trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(),
+		.cntr.reg_cntr_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(),
+		.name = "gpc2clk",
+		.scale = 1
+	};
+	clk->namemap_xlat_table[0] = CTRL_CLK_DOMAIN_GPC2CLK;
+	clk->clk_namemap[1] = (struct namemap_cfg) {
+		.namemap = CLK_NAMEMAP_INDEX_SYS2CLK,
+		.is_enable = 1,
+		.is_counter = 1,
+		.g = g,
+		.cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncsyspll_cfg_r(),
+		.cntr.reg_ctrl_idx  = trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(),
+		.cntr.reg_cntr_addr = trim_sys_clk_cntr_ncsyspll_cnt_r(),
+		.name = "sys2clk",
+		.scale = 1
+	};
+	clk->namemap_xlat_table[1] = CTRL_CLK_DOMAIN_SYS2CLK;
+	clk->clk_namemap[2] = (struct namemap_cfg) {
+		.namemap = CLK_NAMEMAP_INDEX_XBAR2CLK,
+		.is_enable = 1,
+		.is_counter = 1,
+		.g = g,
+		.cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncltcpll_cfg_r(),
+		.cntr.reg_ctrl_idx  = trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(),
+		.cntr.reg_cntr_addr = trim_sys_clk_cntr_ncltcpll_cnt_r(),
+		.name = "xbar2clk",
+		.scale = 1
+	};
+	clk->namemap_xlat_table[2] = CTRL_CLK_DOMAIN_XBAR2CLK;
+	clk->clk_namemap[3] = (struct namemap_cfg) {
+		.namemap = CLK_NAMEMAP_INDEX_DRAMCLK,
+		.is_enable = 1,
+		.is_counter = 1,
+		.g = g,
+		.cntr.reg_ctrl_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(),
+		.cntr.reg_ctrl_idx  =
+			trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(),
+		.cntr.reg_cntr_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(),
+		.name = "dramdiv2_rec_clk1",
+		.scale = 2
+	};
+	clk->namemap_xlat_table[3] = CTRL_CLK_DOMAIN_MCLK;
+
+	clk->namemap_num = NUM_NAMEMAPS;
+
+	clk->g = g;
+
+#ifdef CONFIG_DEBUG_FS
+	if (!clk->debugfs_set) {
+		if (!clk_gp106_debugfs_init(g))
+			clk->debugfs_set = true;
+	}
+#endif
+	return err;
+}
+
+static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
+	u32 save_reg;
+	u32 retries;
+	u32 cntr = 0;
+
+	struct clk_gk20a *clk = &g->clk;
+
+	if (!c || !c->cntr.reg_ctrl_addr || !c->cntr.reg_cntr_addr)
+		return 0;
+
+	mutex_lock(&clk->clk_mutex);
+
+	/* Save the register */
+	save_reg = gk20a_readl(g, c->cntr.reg_ctrl_addr);
+
+	/* Disable and reset the current clock */
+	gk20a_writel(g, c->cntr.reg_ctrl_addr,
+				 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() |
+				 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f());
+
+	/* Force wb() */
+	gk20a_readl(g, c->cntr.reg_ctrl_addr);
+
+	/* Wait for reset to happen */
+	retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES;
+	do {
+		udelay(CLK_DEFAULT_CNTRL_SETTLE_USECS);
+	} while ((--retries) && (cntr = gk20a_readl(g, c->cntr.reg_cntr_addr)));
+
+	if (!retries) {
+		gk20a_err(dev_from_gk20a(g),
+             "unable to settle counter reset, bailing");
+		goto read_err;
+	}
+	/* Program counter */
+	gk20a_writel(g, c->cntr.reg_ctrl_addr,
+					trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f()          |
+				 	trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f()           |
+				 	trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f()         |
+				 	trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f()         |
+				 	trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f()         |
+				 	trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS)  |
+					c->cntr.reg_ctrl_idx);
+	gk20a_readl(g, c->cntr.reg_ctrl_addr);
+
+	udelay(XTAL_CNTR_DELAY);
+
+	cntr = XTAL_SCALE_TO_KHZ * gk20a_readl(g, c->cntr.reg_cntr_addr);
+
+read_err:
+	/* reset and restore control register */
+	gk20a_writel(g, c->cntr.reg_ctrl_addr,
+				 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() |
+				 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f());
+	gk20a_readl(g, c->cntr.reg_ctrl_addr);
+	gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg);
+	gk20a_readl(g, c->cntr.reg_ctrl_addr);
+	mutex_unlock(&clk->clk_mutex);
+
+	return cntr;
+
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int gp106_get_rate_show(void *data , u64 *val) {
+	struct namemap_cfg *c = (struct namemap_cfg *) data;
+	struct gk20a *g = c->g;
+
+	*val = c->is_counter ? gp106_get_rate_cntr(g, c) : 0 /* TODO PLL read */;
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n");
+
+
+static int clk_gp106_debugfs_init(struct gk20a *g) {
+	struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+
+	struct dentry *gpu_root = platform->debugfs;
+	struct dentry *clocks_root;
+	struct dentry *d;
+	unsigned int i;
+
+	if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root)))
+		return -ENOMEM;
+
+	gk20a_dbg(gpu_dbg_info, "g=%p", g);
+
+	for (i = 0; i < g->clk.namemap_num; i++) {
+		if (g->clk.clk_namemap[i].is_enable) {
+			d = debugfs_create_file(
+				g->clk.clk_namemap[i].name,
+				S_IRUGO,
+				clocks_root,
+				&g->clk.clk_namemap[i],
+				&get_rate_fops);
+			if (!d)
+				goto err_out;
+		}
+	}
+	return 0;
+
+err_out:
+	pr_err("%s: Failed to make debugfs node\n", __func__);
+	debugfs_remove_recursive(clocks_root);
+	return -ENOMEM;
+}
+#endif /* CONFIG_DEBUG_FS */
+
+void gp106_init_clk_ops(struct gpu_ops *gops) {
+	gops->clk.init_clk_support = gp106_init_clk_support;
+	gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz;
+	gops->clk.get_rate = gp106_clk_get_rate;
+}
+

drivers/gpu/nvgpu/gp106/clk_gp106.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef CLK_GP106_H
+#define CLK_GP106_H
+
+#include <linux/mutex.h>
+
+#define CLK_NAMEMAP_INDEX_GPC2CLK	0x00
+#define CLK_NAMEMAP_INDEX_XBAR2CLK	0x02
+#define CLK_NAMEMAP_INDEX_SYS2CLK	0x07	/* SYSPLL */
+#define CLK_NAMEMAP_INDEX_DRAMCLK	0x20	/* DRAMPLL */
+
+#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
+#define CLK_DEFAULT_CNTRL_SETTLE_USECS   5
+
+#define XTAL_CNTR_CLKS		27000	/* 1000usec at 27KHz XTAL */
+#define XTAL_CNTR_DELAY		1000	/* we need acuracy up to the ms   */
+#define XTAL_SCALE_TO_KHZ	1
+
+
+
+struct namemap_cfg {
+	u32 namemap;
+	u32 is_enable;	/* Namemap enabled */
+	u32 is_counter;	/* Using cntr */
+	struct gk20a *g;
+	union {
+		struct {
+			u32 reg_ctrl_addr;
+			u32 reg_ctrl_idx;
+			u32 reg_cntr_addr;
+		} cntr;
+		struct {
+			/* Todo */
+		} pll;
+	};
+	u32 scale;
+	char name[24];
+};
+
+void gp106_init_clk_ops(struct gpu_ops *gops);
+
+#endif /* CLK_GP106_H */

drivers/gpu/nvgpu/gp106/fb_gp106.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include "gk20a/gk20a.h"
+#include "gp10b/fb_gp10b.h"
+#include "hw_fb_gp106.h"
+
+#define HW_SCRUB_TIMEOUT_DEFAULT	100 /* usec */
+#define HW_SCRUB_TIMEOUT_MAX		2000000 /* usec */
+
+static void gp106_fb_reset(struct gk20a *g)
+{
+	int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT;
+	/* wait for memory to be accessible */
+	do {
+		u32 w = gk20a_readl(g, fb_niso_scrub_status_r());
+		if (fb_niso_scrub_status_flag_v(w)) {
+			gk20a_dbg_fn("done");
+			break;
+		}
+		udelay(HW_SCRUB_TIMEOUT_DEFAULT);
+	} while (--retries);
+}
+
+void gp106_init_fb(struct gpu_ops *gops)
+{
+	gp10b_init_fb(gops);
+
+	gops->fb.init_fs_state = NULL;
+	gops->fb.reset = gp106_fb_reset;
+}

drivers/gpu/nvgpu/gp106/fb_gp106.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef FB_GP106_H
+#define FB_GP106_H
+struct gpu_ops;
+
+void gp106_init_fb(struct gpu_ops *gops);
+#endif

drivers/gpu/nvgpu/gp106/fifo_gp106.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gp10b/fifo_gp10b.h"
+#include "fifo_gp106.h"
+#include "hw_ccsr_gp106.h"
+#include "hw_fifo_gp106.h"
+
+static u32 gp106_fifo_get_num_fifos(struct gk20a *g)
+{
+	return ccsr_channel__size_1_v();
+}
+
+void gp106_init_fifo(struct gpu_ops *gops)
+{
+	gp10b_init_fifo(gops);
+	gops->fifo.get_num_fifos = gp106_fifo_get_num_fifos;
+	gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
+}

drivers/gpu/nvgpu/gp106/fifo_gp106.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef NVGPU_FIFO_GP106_H
+#define NVGPU_FIFO_GP106_H
+struct gpu_ops;
+void gp106_init_fifo(struct gpu_ops *gops);
+#endif

drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c

@@ -0,0 +1,649 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#ifndef __gp106_gating_reglist_h__
+#define __gp106_gating_reglist_h__
+
+#include <linux/types.h>
+#include "gp106_gating_reglist.h"
+
+struct gating_desc {
+	u32 addr;
+	u32 prod;
+	u32 disable;
+};
+/* slcg bus */
+static const struct gating_desc gp106_slcg_bus[] = {
+	{.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
+};
+
+/* slcg ce2 */
+static const struct gating_desc gp106_slcg_ce2[] = {
+	{.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
+};
+
+/* slcg chiplet */
+static const struct gating_desc gp106_slcg_chiplet[] = {
+	{.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010c1fc, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010c2fc, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010d1fc, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010d2fc, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
+};
+
+/* slcg fb */
+static const struct gating_desc gp106_slcg_fb[] = {
+	{.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
+};
+
+/* slcg fifo */
+static const struct gating_desc gp106_slcg_fifo[] = {
+	{.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe},
+};
+
+/* slcg gr */
+static const struct gating_desc gp106_slcg_gr[] = {
+	{.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe},
+	{.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
+	{.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
+	{.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
+	{.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
+	{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
+	{.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
+	{.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
+	{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
+	{.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe},
+	{.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
+	{.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},
+	{.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe},
+	{.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
+	{.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
+	{.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
+	{.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
+	{.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
+	{.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
+	{.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
+	{.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
+	{.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
+	{.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
+	{.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
+	{.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
+	{.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
+	{.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
+	{.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
+	{.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
+	{.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
+	{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
+	{.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x0000ffff},
+	{.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x0000ffff},
+	{.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
+};
+
+/* slcg ltc */
+static const struct gating_desc gp106_slcg_ltc[] = {
+	{.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
+};
+
+/* slcg perf */
+static const struct gating_desc gp106_slcg_perf[] = {
+	{.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001bc418, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001bc618, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001bc818, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001bca18, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b8418, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b8618, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b8818, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b8a18, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
+};
+
+/* slcg PriRing */
+static const struct gating_desc gp106_slcg_priring[] = {
+	{.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
+};
+
+/* slcg pmu */
+static const struct gating_desc gp106_slcg_pmu[] = {
+	{.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
+	{.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe},
+	{.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* therm gr */
+static const struct gating_desc gp106_slcg_therm[] = {
+	{.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* slcg Xbar */
+static const struct gating_desc gp106_slcg_xbar[] = {
+	{.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe},
+	{.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe},
+	{.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
+	{.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
+	{.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe},
+	{.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe},
+	{.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe},
+	{.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe},
+	{.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe},
+};
+
+/* blcg bus */
+static const struct gating_desc gp106_blcg_bus[] = {
+	{.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
+};
+
+/* blcg ce */
+static const struct gating_desc gp106_blcg_ce[] = {
+	{.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg fb */
+static const struct gating_desc gp106_blcg_fb[] = {
+	{.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
+	{.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
+};
+
+/* blcg fifo */
+static const struct gating_desc gp106_blcg_fifo[] = {
+	{.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg gr */
+static const struct gating_desc gp106_blcg_gr[] = {
+	{.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
+	{.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
+	{.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
+	{.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
+	{.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
+	{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
+	{.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
+	{.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
+	{.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
+	{.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
+	{.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
+	{.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
+	{.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
+	{.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
+	{.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
+	{.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
+	{.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
+	{.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
+	{.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
+	{.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
+	{.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
+	{.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
+	{.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg ltc */
+static const struct gating_desc gp106_blcg_ltc[] = {
+	{.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
+};
+
+/* blcg pmu */
+static const struct gating_desc gp106_blcg_pmu[] = {
+	{.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
+};
+
+/* blcg Xbar */
+static const struct gating_desc gp106_blcg_xbar[] = {
+	{.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000},
+	{.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000},
+	{.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000},
+	{.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000},
+};
+
+/* pg gr */
+static const struct gating_desc gp106_pg_gr[] = {
+};
+
+/* inline functions */
+void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_bus[i].addr,
+				gp106_slcg_bus[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_bus[i].addr,
+				 gp106_slcg_bus[i].disable);
+	}
+}
+
+void gp106_slcg_ce2_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_ce2[i].addr,
+				gp106_slcg_ce2[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_ce2[i].addr,
+				 gp106_slcg_ce2[i].disable);
+	}
+}
+
+void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_chiplet[i].addr,
+				gp106_slcg_chiplet[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_chiplet[i].addr,
+				 gp106_slcg_chiplet[i].disable);
+	}
+}
+
+void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+}
+
+void gp106_slcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_fb[i].addr,
+				gp106_slcg_fb[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_fb[i].addr,
+				 gp106_slcg_fb[i].disable);
+	}
+}
+
+void gp106_slcg_fifo_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_fifo[i].addr,
+				gp106_slcg_fifo[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_fifo[i].addr,
+				 gp106_slcg_fifo[i].disable);
+	}
+}
+
+void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_gr[i].addr,
+				gp106_slcg_gr[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_gr[i].addr,
+				 gp106_slcg_gr[i].disable);
+	}
+}
+
+void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_ltc[i].addr,
+				gp106_slcg_ltc[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_ltc[i].addr,
+				gp106_slcg_ltc[i].disable);
+	}
+}
+
+void gp106_slcg_perf_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_perf[i].addr,
+				gp106_slcg_perf[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_perf[i].addr,
+				gp106_slcg_perf[i].disable);
+	}
+}
+
+void gp106_slcg_priring_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_priring[i].addr,
+				gp106_slcg_priring[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_priring[i].addr,
+				gp106_slcg_priring[i].disable);
+	}
+}
+
+void gp106_slcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_pmu[i].addr,
+				gp106_slcg_pmu[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_pmu[i].addr,
+				gp106_slcg_pmu[i].disable);
+	}
+}
+
+void gp106_slcg_therm_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_therm[i].addr,
+				gp106_slcg_therm[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_therm[i].addr,
+				gp106_slcg_therm[i].disable);
+	}
+}
+
+void gp106_slcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_slcg_xbar[i].addr,
+				gp106_slcg_xbar[i].prod);
+		else
+			gk20a_writel(g, gp106_slcg_xbar[i].addr,
+				gp106_slcg_xbar[i].disable);
+	}
+}
+
+void gp106_blcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_blcg_bus[i].addr,
+				gp106_blcg_bus[i].prod);
+		else
+			gk20a_writel(g, gp106_blcg_bus[i].addr,
+				gp106_blcg_bus[i].disable);
+	}
+}
+
+void gp106_blcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_blcg_ce[i].addr,
+				gp106_blcg_ce[i].prod);
+		else
+			gk20a_writel(g, gp106_blcg_ce[i].addr,
+				gp106_blcg_ce[i].disable);
+	}
+}
+
+void gp106_blcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_blcg_fb[i].addr,
+				gp106_blcg_fb[i].prod);
+		else
+			gk20a_writel(g, gp106_blcg_fb[i].addr,
+				gp106_blcg_fb[i].disable);
+	}
+}
+
+void gp106_blcg_fifo_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_blcg_fifo[i].addr,
+				gp106_blcg_fifo[i].prod);
+		else
+			gk20a_writel(g, gp106_blcg_fifo[i].addr,
+				gp106_blcg_fifo[i].disable);
+	}
+}
+
+void gp106_blcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_blcg_gr[i].addr,
+				gp106_blcg_gr[i].prod);
+		else
+			gk20a_writel(g, gp106_blcg_gr[i].addr,
+				gp106_blcg_gr[i].disable);
+	}
+}
+
+void gp106_blcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_blcg_ltc[i].addr,
+				gp106_blcg_ltc[i].prod);
+		else
+			gk20a_writel(g, gp106_blcg_ltc[i].addr,
+				gp106_blcg_ltc[i].disable);
+	}
+}
+
+void gp106_blcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_blcg_pmu[i].addr,
+				gp106_blcg_pmu[i].prod);
+		else
+			gk20a_writel(g, gp106_blcg_pmu[i].addr,
+				gp106_blcg_pmu[i].disable);
+	}
+}
+
+void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_blcg_xbar[i].addr,
+				gp106_blcg_xbar[i].prod);
+		else
+			gk20a_writel(g, gp106_blcg_xbar[i].addr,
+				gp106_blcg_xbar[i].disable);
+	}
+}
+
+void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp106_pg_gr[i].addr,
+				gp106_pg_gr[i].prod);
+		else
+			gk20a_writel(g, gp106_pg_gr[i].addr,
+				gp106_pg_gr[i].disable);
+	}
+}
+
+#endif /* __gp106_gating_reglist_h__ */

drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "gk20a/gk20a.h"
+
+void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_ce2_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_fifo_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_perf_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_priring_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_therm_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_slcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_fifo_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+

drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c

@@ -0,0 +1,50 @@
+/*
+ * GP106 Graphics Context
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gr_ctx_gp106.h"
+#include "nvgpu_gpuid_t18x.h"
+
+static int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name)
+{
+	u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
+
+	switch (ver) {
+		case NVGPU_GPUID_GP104:
+			sprintf(name, "%s/%s", "gp104",
+					GP104_NETLIST_IMAGE_FW_NAME);
+			break;
+		case NVGPU_GPUID_GP106:
+			sprintf(name, "%s/%s", "gp106",
+					GP106_NETLIST_IMAGE_FW_NAME);
+			break;
+		default:
+			gk20a_err(g->dev, "no support for GPUID %x", ver);
+	}
+
+	return 0;
+}
+
+static bool gr_gp106_is_firmware_defined(void)
+{
+	return true;
+}
+
+void gp106_init_gr_ctx(struct gpu_ops *gops)
+{
+	gops->gr_ctx.get_netlist_name = gr_gp106_get_netlist_name;
+	gops->gr_ctx.is_fw_defined = gr_gp106_is_firmware_defined;
+	gops->gr_ctx.use_dma_for_fw_bootstrap = false;
+}

drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __GR_CTX_GP106_H__
+#define __GR_CTX_GP106_H__
+
+#include "gk20a/gr_ctx_gk20a.h"
+
+/* production netlist, one and only one from below */
+#define GP106_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_C
+#define GP104_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D
+
+void gp106_init_gr_ctx(struct gpu_ops *gops);
+
+#endif /*__GR_CTX_GP106_H__*/

drivers/gpu/nvgpu/gp106/gr_gp106.c

@@ -0,0 +1,239 @@
+/*
+ * GP106 GPU GR
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
+
+#include "gk20a/gr_gk20a.h"
+
+#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */
+#include "gp10b/gr_gp10b.h"
+#include "gr_gp106.h"
+#include "hw_gr_gp106.h"
+
+static bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num)
+{
+	bool valid = false;
+
+	switch (class_num) {
+	case PASCAL_COMPUTE_A:
+	case PASCAL_COMPUTE_B:
+	case PASCAL_A:
+	case PASCAL_B:
+	case PASCAL_DMA_COPY_A:
+	case PASCAL_DMA_COPY_B:
+		valid = true;
+		break;
+
+	case MAXWELL_COMPUTE_B:
+	case MAXWELL_B:
+	case FERMI_TWOD_A:
+	case KEPLER_DMA_COPY_A:
+	case MAXWELL_DMA_COPY_A:
+		valid = true;
+		break;
+
+	default:
+		break;
+	}
+	gk20a_dbg_info("class=0x%x valid=%d", class_num, valid);
+	return valid;
+}
+
+static u32 gr_gp106_pagepool_default_size(struct gk20a *g)
+{
+	return gr_scc_pagepool_total_pages_hwmax_value_v();
+}
+
+static void gr_gp106_set_go_idle_timeout(struct gk20a *g, u32 data)
+{
+	gk20a_writel(g, gr_fe_go_idle_timeout_r(), data);
+}
+
+static int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
+				     u32 class_num, u32 offset, u32 data)
+{
+	gk20a_dbg_fn("");
+
+	if (class_num == PASCAL_COMPUTE_B) {
+		switch (offset << 2) {
+		case NVC0C0_SET_SHADER_EXCEPTIONS:
+			gk20a_gr_set_shader_exceptions(g, data);
+			break;
+		default:
+			goto fail;
+		}
+	}
+
+	if (class_num == PASCAL_B) {
+		switch (offset << 2) {
+		case NVC097_SET_SHADER_EXCEPTIONS:
+			gk20a_gr_set_shader_exceptions(g, data);
+			break;
+		case NVC097_SET_CIRCULAR_BUFFER_SIZE:
+			g->ops.gr.set_circular_buffer_size(g, data);
+			break;
+		case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
+			g->ops.gr.set_alpha_circular_buffer_size(g, data);
+			break;
+		case NVC097_SET_GO_IDLE_TIMEOUT:
+			gr_gp106_set_go_idle_timeout(g, data);
+			break;
+		default:
+			goto fail;
+		}
+	}
+	return 0;
+
+fail:
+	return -EINVAL;
+}
+
+static void gr_gp106_cb_size_default(struct gk20a *g)
+{
+	struct gr_gk20a *gr = &g->gr;
+
+	if (!gr->attrib_cb_default_size)
+		gr->attrib_cb_default_size = 0x800;
+	gr->alpha_cb_default_size =
+		gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
+}
+
+static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
+				struct gr_ctx_desc *gr_ctx,
+				struct vm_gk20a *vm, u32 class,
+				u32 graphics_preempt_mode,
+				u32 compute_preempt_mode)
+{
+	int err = 0;
+
+	if (class == PASCAL_B && g->gr.t18x.ctx_vars.force_preemption_gfxp)
+		graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
+
+	if (class == PASCAL_COMPUTE_B &&
+			g->gr.t18x.ctx_vars.force_preemption_cilp)
+		compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
+
+	/* check for invalid combinations */
+	if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0))
+		return -EINVAL;
+
+	if ((graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) &&
+		   (compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP))
+		return -EINVAL;
+
+	/* set preemption modes */
+	switch (graphics_preempt_mode) {
+	case NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP:
+		{
+		u32 spill_size =
+			gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
+			gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
+		u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
+			gr_scc_pagepool_total_pages_byte_granularity_v();
+		u32 betacb_size = g->gr.attrib_cb_default_size +
+				  (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
+				   gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
+		u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
+				  gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
+				  g->gr.max_tpc_count;
+		attrib_cb_size = ALIGN(attrib_cb_size, 128);
+
+		gk20a_dbg_info("gfxp context spill_size=%d", spill_size);
+		gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size);
+		gk20a_dbg_info("gfxp context attrib_cb_size=%d",
+				attrib_cb_size);
+
+		err = gr_gp10b_alloc_buffer(vm,
+					g->gr.t18x.ctx_vars.preempt_image_size,
+					&gr_ctx->t18x.preempt_ctxsw_buffer);
+		if (err) {
+			gk20a_err(dev_from_gk20a(g),
+				  "cannot allocate preempt buffer");
+			goto fail;
+		}
+
+		err = gr_gp10b_alloc_buffer(vm,
+					spill_size,
+					&gr_ctx->t18x.spill_ctxsw_buffer);
+		if (err) {
+			gk20a_err(dev_from_gk20a(g),
+				  "cannot allocate spill buffer");
+			goto fail_free_preempt;
+		}
+
+		err = gr_gp10b_alloc_buffer(vm,
+					attrib_cb_size,
+					&gr_ctx->t18x.betacb_ctxsw_buffer);
+		if (err) {
+			gk20a_err(dev_from_gk20a(g),
+				  "cannot allocate beta buffer");
+			goto fail_free_spill;
+		}
+
+		err = gr_gp10b_alloc_buffer(vm,
+					pagepool_size,
+					&gr_ctx->t18x.pagepool_ctxsw_buffer);
+		if (err) {
+			gk20a_err(dev_from_gk20a(g),
+				  "cannot allocate page pool");
+			goto fail_free_betacb;
+		}
+
+		gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
+		break;
+		}
+
+	case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI:
+		gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
+		break;
+
+	default:
+		break;
+	}
+
+	if (class == PASCAL_COMPUTE_B) {
+		switch (compute_preempt_mode) {
+		case NVGPU_COMPUTE_PREEMPTION_MODE_WFI:
+		case NVGPU_COMPUTE_PREEMPTION_MODE_CTA:
+		case NVGPU_COMPUTE_PREEMPTION_MODE_CILP:
+			gr_ctx->compute_preempt_mode = compute_preempt_mode;
+			break;
+		default:
+			break;
+		}
+	}
+
+	return 0;
+
+fail_free_betacb:
+	gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
+fail_free_spill:
+	gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
+fail_free_preempt:
+	gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
+fail:
+	return err;
+}
+
+void gp106_init_gr(struct gpu_ops *gops)
+{
+	gp10b_init_gr(gops);
+	gops->gr.is_valid_class = gr_gp106_is_valid_class;
+	gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size;
+	gops->gr.handle_sw_method = gr_gp106_handle_sw_method;
+	gops->gr.cb_size_default = gr_gp106_cb_size_default;
+	gops->gr.init_preemption_state = NULL;
+	gops->gr.set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode;
+}

drivers/gpu/nvgpu/gp106/gr_gp106.h

@@ -0,0 +1,26 @@
+/*
+ * GP106 GPU GR
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_GR_GP106_H_
+#define _NVGPU_GR_GP106_H_
+
+enum {
+	PASCAL_B                 = 0xC197,
+	PASCAL_COMPUTE_B         = 0xC1C0,
+};
+
+void gp106_init_gr(struct gpu_ops *gops);
+
+#endif

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -0,0 +1,259 @@
+/*
+ * GP106 HAL interface
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/printk.h>
+
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+
+#include "gp10b/gr_gp10b.h"
+#include "gp10b/mc_gp10b.h"
+#include "gp106/ltc_gp106.h"
+#include "gp10b/mm_gp10b.h"
+#include "gp10b/ce_gp10b.h"
+#include "gp106/fifo_gp106.h"
+#include "gp106/regops_gp106.h"
+#include "gp10b/cde_gp10b.h"
+#include "gp106/therm_gp106.h"
+#include "gp106/xve_gp106.h"
+
+#include "gp106/bios_gp106.h"
+
+#include "gm20b/gr_gm20b.h"
+#include "gm20b/fifo_gm20b.h"
+#include "gm20b/pmu_gm20b.h"
+#include "gp106/clk_gp106.h"
+#include "gp106/clk_arb_gp106.h"
+
+#include "gp106/mm_gp106.h"
+#include "gp106/pmu_gp106.h"
+#include "gp106/gr_ctx_gp106.h"
+#include "gp106/gr_gp106.h"
+#include "gp106/fb_gp106.h"
+#include "gp106/gp106_gating_reglist.h"
+#include "nvgpu_gpuid_t18x.h"
+#include "hw_proj_gp106.h"
+#include "gk20a/dbg_gpu_gk20a.h"
+#include "gk20a/css_gr_gk20a.h"
+
+static struct gpu_ops gp106_ops = {
+	.clock_gating = {
+		.slcg_bus_load_gating_prod =
+			gp106_slcg_bus_load_gating_prod,
+		.slcg_ce2_load_gating_prod =
+			gp106_slcg_ce2_load_gating_prod,
+		.slcg_chiplet_load_gating_prod =
+			gp106_slcg_chiplet_load_gating_prod,
+		.slcg_ctxsw_firmware_load_gating_prod =
+			gp106_slcg_ctxsw_firmware_load_gating_prod,
+		.slcg_fb_load_gating_prod =
+			gp106_slcg_fb_load_gating_prod,
+		.slcg_fifo_load_gating_prod =
+			gp106_slcg_fifo_load_gating_prod,
+		.slcg_gr_load_gating_prod =
+			gr_gp106_slcg_gr_load_gating_prod,
+		.slcg_ltc_load_gating_prod =
+			ltc_gp106_slcg_ltc_load_gating_prod,
+		.slcg_perf_load_gating_prod =
+			gp106_slcg_perf_load_gating_prod,
+		.slcg_priring_load_gating_prod =
+			gp106_slcg_priring_load_gating_prod,
+		.slcg_pmu_load_gating_prod =
+			gp106_slcg_pmu_load_gating_prod,
+		.slcg_therm_load_gating_prod =
+			gp106_slcg_therm_load_gating_prod,
+		.slcg_xbar_load_gating_prod =
+			gp106_slcg_xbar_load_gating_prod,
+		.blcg_bus_load_gating_prod =
+			gp106_blcg_bus_load_gating_prod,
+		.blcg_ce_load_gating_prod =
+			gp106_blcg_ce_load_gating_prod,
+		.blcg_fb_load_gating_prod =
+			gp106_blcg_fb_load_gating_prod,
+		.blcg_fifo_load_gating_prod =
+			gp106_blcg_fifo_load_gating_prod,
+		.blcg_gr_load_gating_prod =
+			gp106_blcg_gr_load_gating_prod,
+		.blcg_ltc_load_gating_prod =
+			gp106_blcg_ltc_load_gating_prod,
+		.blcg_pmu_load_gating_prod =
+			gp106_blcg_pmu_load_gating_prod,
+		.blcg_xbar_load_gating_prod =
+			gp106_blcg_xbar_load_gating_prod,
+		.pg_gr_load_gating_prod =
+			gr_gp106_pg_gr_load_gating_prod,
+		}
+};
+
+static int gp106_get_litter_value(struct gk20a *g, int value)
+{
+	int ret = -EINVAL;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_BASE:
+		ret = proj_ppc_in_gpc_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+		ret = proj_ppc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_ENGINES:
+		ret = proj_host_num_engines_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	case GPU_LIT_FBPA_SHARED_BASE:
+		ret = proj_fbpa_shared_base_v();
+		break;
+	case GPU_LIT_FBPA_BASE:
+		ret = proj_fbpa_base_v();
+		break;
+	case GPU_LIT_FBPA_STRIDE:
+		ret = proj_fbpa_stride_v();
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	return ret;
+}
+
+int gp106_init_gpu_characteristics(struct gk20a *g)
+{
+	struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
+
+	int err;
+
+	err = gk20a_init_gpu_characteristics(g);
+	if (err)
+		return err;
+
+	gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE |
+			NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT |
+			NVGPU_GPU_FLAGS_SUPPORT_GET_POWER |
+			NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE;
+
+	return 0;
+}
+
+int gp106_init_hal(struct gk20a *g)
+{
+	struct gpu_ops *gops = &g->ops;
+	struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
+
+	gk20a_dbg_fn("");
+
+	*gops = gp106_ops;
+
+	gops->privsecurity = 1;
+	gops->securegpccs = 1;
+	gops->pmupstate = true;
+	gp10b_init_mc(gops);
+	gp106_init_gr(gops);
+	gp106_init_ltc(gops);
+	gp106_init_fb(gops);
+	gp106_init_fifo(gops);
+	gp10b_init_ce(gops);
+	gp106_init_gr_ctx(gops);
+	gp106_init_mm(gops);
+	gp106_init_pmu_ops(gops);
+	gk20a_init_debug_ops(gops);
+	gk20a_init_dbg_session_ops(gops);
+	gp106_init_clk_ops(gops);
+	gp106_init_clk_arb_ops(gops);
+	gp106_init_regops(gops);
+	gp10b_init_cde_ops(gops);
+	gk20a_init_tsg_ops(gops);
+#if defined(CONFIG_GK20A_CYCLE_STATS)
+	gk20a_init_css_ops(gops);
+#endif
+	gp106_init_bios(gops);
+	gp106_init_therm_ops(gops);
+	gp106_init_xve_ops(gops);
+
+	gops->name = "gp10x";
+	gops->get_litter_value = gp106_get_litter_value;
+	gops->chip_init_gpu_characteristics = gp106_init_gpu_characteristics;
+	gops->gr_ctx.use_dma_for_fw_bootstrap = true;
+	gops->read_ptimer = gk20a_read_ptimer;
+
+	c->twod_class = FERMI_TWOD_A;
+	c->threed_class = PASCAL_B;
+	c->compute_class = PASCAL_COMPUTE_B;
+	c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
+	c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
+	c->dma_copy_class = PASCAL_DMA_COPY_A;
+
+	gk20a_dbg_fn("done");
+
+	return 0;
+}

drivers/gpu/nvgpu/gp106/hal_gp106.h

@@ -0,0 +1,21 @@
+/*
+ * GP106 Tegra HAL interface
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_HAL_GP106_H
+#define _NVGPU_HAL_GP106_H
+struct gk20a;
+
+int gp106_init_hal(struct gk20a *gops);
+#endif

drivers/gpu/nvgpu/gp106/hw_bus_gp106.h

@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_bus_gp106_h_
+#define _hw_bus_gp106_h_
+
+static inline u32 bus_bar1_block_r(void)
+{
+	return 0x00001704;
+}
+static inline u32 bus_bar1_block_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 bus_bar1_block_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 bus_bar1_block_mode_virtual_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 bus_bar2_block_r(void)
+{
+	return 0x00001714;
+}
+static inline u32 bus_bar2_block_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 bus_bar2_block_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 bus_bar2_block_mode_virtual_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 bus_bar1_block_ptr_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 bus_bar2_block_ptr_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 bus_bind_status_r(void)
+{
+	return 0x00001710;
+}
+static inline u32 bus_bind_status_bar1_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 bus_bind_status_bar1_pending_empty_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bind_status_bar1_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
+{
+	return 0x2;
+}
+static inline u32 bus_bind_status_bar2_pending_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 bus_bind_status_bar2_pending_empty_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bind_status_bar2_pending_busy_f(void)
+{
+	return 0x4;
+}
+static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
+{
+	return (r >> 3) & 0x1;
+}
+static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
+{
+	return 0x8;
+}
+static inline u32 bus_intr_0_r(void)
+{
+	return 0x00001100;
+}
+static inline u32 bus_intr_0_pri_squash_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 bus_intr_0_pri_fecserr_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 bus_intr_0_pri_timeout_m(void)
+{
+	return 0x1 << 3;
+}
+static inline u32 bus_intr_en_0_r(void)
+{
+	return 0x00001140;
+}
+static inline u32 bus_intr_en_0_pri_squash_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 bus_intr_en_0_pri_fecserr_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 bus_intr_en_0_pri_timeout_m(void)
+{
+	return 0x1 << 3;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ccsr_gp106_h_
+#define _hw_ccsr_gp106_h_
+
+static inline u32 ccsr_channel_inst_r(u32 i)
+{
+	return 0x00800000 + i*8;
+}
+static inline u32 ccsr_channel_inst__size_1_v(void)
+{
+	return 0x00001000;
+}
+static inline u32 ccsr_channel_inst_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 ccsr_channel_inst_bind_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 ccsr_channel_inst_bind_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 ccsr_channel_r(u32 i)
+{
+	return 0x00800004 + i*8;
+}
+static inline u32 ccsr_channel__size_1_v(void)
+{
+	return 0x00001000;
+}
+static inline u32 ccsr_channel_enable_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ccsr_channel_enable_set_f(u32 v)
+{
+	return (v & 0x1) << 10;
+}
+static inline u32 ccsr_channel_enable_set_true_f(void)
+{
+	return 0x400;
+}
+static inline u32 ccsr_channel_enable_clr_true_f(void)
+{
+	return 0x800;
+}
+static inline u32 ccsr_channel_status_v(u32 r)
+{
+	return (r >> 24) & 0xf;
+}
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_ce_gp106.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce_gp106_h_
+#define _hw_ce_gp106_h_
+
+static inline u32 ce_intr_status_r(u32 i)
+{
+	return 0x00104410 + i*128;
+}
+static inline u32 ce_intr_status_blockpipe_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ce_intr_status_blockpipe_reset_f(void)
+{
+	return 0x1;
+}
+static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
+{
+	return 0x2;
+}
+static inline u32 ce_intr_status_launcherr_pending_f(void)
+{
+	return 0x4;
+}
+static inline u32 ce_intr_status_launcherr_reset_f(void)
+{
+	return 0x4;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_ctxsw_prog_gp106.h

@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ctxsw_prog_gp106_h_
+#define _hw_ctxsw_prog_gp106_h_
+
+static inline u32 ctxsw_prog_fecs_header_v(void)
+{
+	return 0x00000100;
+}
+static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
+{
+	return 0x00000008;
+}
+static inline u32 ctxsw_prog_main_image_patch_count_o(void)
+{
+	return 0x00000010;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
+{
+	return 0x00000014;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
+{
+	return 0x00000018;
+}
+static inline u32 ctxsw_prog_main_image_zcull_o(void)
+{
+	return 0x0000001c;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
+{
+	return 0x00000020;
+}
+static inline u32 ctxsw_prog_main_image_pm_o(void)
+{
+	return 0x00000028;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
+{
+	return 0x7 << 0;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
+{
+	return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
+{
+	return 0x7 << 3;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
+{
+	return 0x8;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
+{
+	return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
+{
+	return 0x0000002c;
+}
+static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
+{
+	return 0x000000f4;
+}
+static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
+{
+	return 0x000000d0;
+}
+static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
+{
+	return 0x000000d4;
+}
+static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
+{
+	return 0x000000d8;
+}
+static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
+{
+	return 0x000000dc;
+}
+static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
+{
+	return 0x000000f8;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_o(void)
+{
+	return 0x000000fc;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
+{
+	return 0x600dc0de;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
+{
+	return 0x0000000c;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
+{
+	return 0x000000f4;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
+{
+	return (r >> 16) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
+{
+	return 0x000000f8;
+}
+static inline u32 ctxsw_prog_local_magic_value_o(void)
+{
+	return 0x000000fc;
+}
+static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
+{
+	return 0xad0becab;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
+{
+	return 0x000000ec;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
+{
+	return (r >> 16) & 0xff;
+}
+static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
+{
+	return 0x00000100;
+}
+static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+	return 0x000000a0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+	return 2;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
+{
+	return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+	return 0x2;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+	return 0x000000a4;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+	return 0x000000a8;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+	return 0x0000003c;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+	return 0x1 << 3;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
+{
+	return 0x00000080;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
+{
+	return 0x1;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
+{
+	return 0x00000068;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
+{
+	return 0x00000084;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
+{
+	return 0x1;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
+{
+	return 0x2;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_fb_gp106.h

@@ -0,0 +1,609 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fb_gp106_h_
+#define _hw_fb_gp106_h_
+
+static inline u32 fb_fbhub_num_active_ltcs_r(void)
+{
+	return 0x00100800;
+}
+static inline u32 fb_mmu_ctrl_r(void)
+{
+	return 0x00100c80;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
+{
+	return 0x1;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
+{
+	return (r >> 15) & 0x1;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
+{
+	return (r >> 16) & 0xff;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
+{
+	return (r >> 11) & 0x1;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
+{
+	return 0x800;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_priv_mmu_phy_secure_r(void)
+{
+	return 0x00100ce4;
+}
+static inline u32 fb_mmu_invalidate_pdb_r(void)
+{
+	return 0x00100cb8;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
+{
+	return 0x2;
+}
+static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_invalidate_r(void)
+{
+	return 0x00100cbc;
+}
+static inline u32 fb_mmu_invalidate_all_va_true_f(void)
+{
+	return 0x1;
+}
+static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
+{
+	return 0x2;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
+{
+	return 1;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
+{
+	return 0x4;
+}
+static inline u32 fb_mmu_invalidate_replay_s(void)
+{
+	return 3;
+}
+static inline u32 fb_mmu_invalidate_replay_f(u32 v)
+{
+	return (v & 0x7) << 3;
+}
+static inline u32 fb_mmu_invalidate_replay_m(void)
+{
+	return 0x7 << 3;
+}
+static inline u32 fb_mmu_invalidate_replay_v(u32 r)
+{
+	return (r >> 3) & 0x7;
+}
+static inline u32 fb_mmu_invalidate_replay_none_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_invalidate_replay_start_f(void)
+{
+	return 0x8;
+}
+static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
+{
+	return 0x10;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
+{
+	return 0x18;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
+{
+	return 0x20;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
+{
+	return 0x20;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_s(void)
+{
+	return 1;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_m(void)
+{
+	return 0x1 << 6;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
+{
+	return (r >> 6) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
+{
+	return 0x40;
+}
+static inline u32 fb_mmu_invalidate_ack_s(void)
+{
+	return 2;
+}
+static inline u32 fb_mmu_invalidate_ack_f(u32 v)
+{
+	return (v & 0x3) << 7;
+}
+static inline u32 fb_mmu_invalidate_ack_m(void)
+{
+	return 0x3 << 7;
+}
+static inline u32 fb_mmu_invalidate_ack_v(u32 r)
+{
+	return (r >> 7) & 0x3;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
+{
+	return 0x100;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
+{
+	return 0x80;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
+{
+	return 6;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
+{
+	return (v & 0x3f) << 9;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
+{
+	return 0x3f << 9;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
+{
+	return (r >> 9) & 0x3f;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
+{
+	return 5;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
+{
+	return (v & 0x1f) << 15;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
+{
+	return 0x1f << 15;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
+{
+	return (r >> 15) & 0x1f;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
+{
+	return 1;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
+{
+	return (v & 0x1) << 20;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
+{
+	return 0x1 << 20;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
+{
+	return (r >> 20) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
+{
+	return 0x100000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
+{
+	return 3;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
+{
+	return (v & 0x7) << 24;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
+{
+	return 0x7 << 24;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
+{
+	return (r >> 24) & 0x7;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
+{
+	return 0x3000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
+{
+	return 0x4000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
+{
+	return 0x5000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
+{
+	return 0x6000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
+{
+	return 0x7000000;
+}
+static inline u32 fb_mmu_invalidate_trigger_s(void)
+{
+	return 1;
+}
+static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 fb_mmu_invalidate_trigger_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_trigger_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 fb_mmu_debug_wr_r(void)
+{
+	return 0x00100cc8;
+}
+static inline u32 fb_mmu_debug_wr_aperture_s(void)
+{
+	return 2;
+}
+static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
+{
+	return 0x2;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
+{
+	return 0x3;
+}
+static inline u32 fb_mmu_debug_wr_vol_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_f(void)
+{
+	return 0x4;
+}
+static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 fb_mmu_debug_rd_r(void)
+{
+	return 0x00100ccc;
+}
+static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
+{
+	return 0x2;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
+{
+	return 0x3;
+}
+static inline u32 fb_mmu_debug_rd_vol_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 fb_mmu_debug_ctrl_r(void)
+{
+	return 0x00100cc4;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
+{
+	return (r >> 16) & 0x1;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_m(void)
+{
+	return 0x1 << 16;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
+{
+	return 0x10000;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_vpr_info_r(void)
+{
+	return 0x00100cd0;
+}
+static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+	return 0x00100c10;
+}
+static inline u32 fb_mmu_local_memory_range_r(void)
+{
+	return 0x00100ce0;
+}
+static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r)
+{
+	return (r >> 0) & 0xf;
+}
+static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r)
+{
+	return (r >> 4) & 0x3f;
+}
+static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 fb_fbpa_fbio_delay_r(void)
+{
+	return 0x9a065c;
+}
+static inline u32 fb_fbpa_fbio_delay_src_m(void)
+{
+	return 0x7;
+}
+static inline u32 fb_fbpa_fbio_delay_src_v(u32 r)
+{
+	return (r >> 0) & 0x7;
+}
+static inline u32 fb_fbpa_fbio_delay_src_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 fb_fbpa_fbio_delay_src_max_v(void)
+{
+	return 2;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_m(void)
+{
+	return 0x7 << 4;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r)
+{
+	return (r >> 4) & 0x7;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v)
+{
+	return (v & 0x7) << 4;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_max_v(void)
+{
+	return 2;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_r(void)
+{
+	return 0x9a08e0;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void)
+{
+	return 0x7;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r)
+{
+	return (r >> 0) & 0x7;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void)
+{
+	return 1;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void)
+{
+	return 0x7 << 4;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r)
+{
+	return (r >> 4) & 0x7;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v)
+{
+	return (v & 0x7) << 4;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void)
+{
+	return 1;
+}
+static inline u32 fb_niso_scrubber_status_r(void)
+{
+	return 0x00100b20;
+}
+static inline u32 fb_niso_scrubber_status_flag_s(void)
+{
+	return 1;
+}
+static inline u32 fb_niso_scrubber_status_flag_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 fb_niso_scrubber_status_flag_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 fb_niso_scrubber_status_flag_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 fb_niso_scrub_status_r(void)
+{
+	return 0x00100b20;
+}
+static inline u32 fb_niso_scrub_status_flag_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 fb_fbpa_fbio_iref_byte_rx_ctrl_r(void)
+{
+	return 0x009a0eb0;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_fbpa_gp106.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fbpa_gp106_h_
+#define _hw_fbpa_gp106_h_
+
+static inline u32 fbpa_cstatus_r(void)
+{
+	return 0x009a020c;
+}
+static inline u32 fbpa_cstatus_ramamount_v(u32 r)
+{
+	return (r >> 0) & 0x1ffff;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_fifo_gp106.h

@@ -0,0 +1,685 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fifo_gp106_h_
+#define _hw_fifo_gp106_h_
+
+static inline u32 fifo_bar1_base_r(void)
+{
+	return 0x00002254;
+}
+static inline u32 fifo_bar1_base_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 fifo_bar1_base_valid_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_bar1_base_valid_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 fifo_runlist_base_r(void)
+{
+	return 0x00002270;
+}
+static inline u32 fifo_runlist_base_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 fifo_runlist_base_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 fifo_runlist_r(void)
+{
+	return 0x00002274;
+}
+static inline u32 fifo_runlist_engine_f(u32 v)
+{
+	return (v & 0xf) << 20;
+}
+static inline u32 fifo_eng_runlist_base_r(u32 i)
+{
+	return 0x00002280 + i*8;
+}
+static inline u32 fifo_eng_runlist_base__size_1_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 fifo_eng_runlist_r(u32 i)
+{
+	return 0x00002284 + i*8;
+}
+static inline u32 fifo_eng_runlist__size_1_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 fifo_eng_runlist_length_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+	return 0x0000ffff;
+}
+static inline u32 fifo_eng_runlist_pending_true_f(void)
+{
+	return 0x100000;
+}
+static inline u32 fifo_pb_timeslice_r(u32 i)
+{
+	return 0x00002350 + i*4;
+}
+static inline u32 fifo_pb_timeslice_timeout_16_f(void)
+{
+	return 0x10;
+}
+static inline u32 fifo_pb_timeslice_timescale_0_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_pb_timeslice_enable_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 fifo_pbdma_map_r(u32 i)
+{
+	return 0x00002390 + i*4;
+}
+static inline u32 fifo_intr_0_r(void)
+{
+	return 0x00002100;
+}
+static inline u32 fifo_intr_0_bind_error_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 fifo_intr_0_bind_error_reset_f(void)
+{
+	return 0x1;
+}
+static inline u32 fifo_intr_0_sched_error_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 fifo_intr_0_sched_error_reset_f(void)
+{
+	return 0x100;
+}
+static inline u32 fifo_intr_0_chsw_error_pending_f(void)
+{
+	return 0x10000;
+}
+static inline u32 fifo_intr_0_chsw_error_reset_f(void)
+{
+	return 0x10000;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
+{
+	return 0x800000;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
+{
+	return 0x800000;
+}
+static inline u32 fifo_intr_0_lb_error_pending_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 fifo_intr_0_lb_error_reset_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 fifo_intr_0_runlist_event_pending_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 fifo_intr_0_channel_intr_pending_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 fifo_intr_en_0_r(void)
+{
+	return 0x00002140;
+}
+static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
+{
+	return (v & 0x1) << 8;
+}
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+	return 0x1 << 8;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
+{
+	return (v & 0x1) << 28;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_m(void)
+{
+	return 0x1 << 28;
+}
+static inline u32 fifo_intr_en_1_r(void)
+{
+	return 0x00002528;
+}
+static inline u32 fifo_intr_bind_error_r(void)
+{
+	return 0x0000252c;
+}
+static inline u32 fifo_intr_sched_error_r(void)
+{
+	return 0x0000254c;
+}
+static inline u32 fifo_intr_sched_error_code_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
+{
+	return 0x0000000a;
+}
+static inline u32 fifo_intr_chsw_error_r(void)
+{
+	return 0x0000256c;
+}
+static inline u32 fifo_intr_mmu_fault_id_r(void)
+{
+	return 0x0000259c;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
+{
+	return 0x00002800 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
+{
+	return (r >> 0) & 0xfffffff;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
+{
+	return 0x00002804 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
+{
+	return 0x00002808 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
+{
+	return 0x0000280c + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
+{
+	return (r >> 20) & 0x1;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
+{
+	return (r >> 8) & 0x7f;
+}
+static inline u32 fifo_intr_pbdma_id_r(void)
+{
+	return 0x000025a0;
+}
+static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
+{
+	return (v & 0x1) << (0 + i*1);
+}
+static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 fifo_intr_runlist_r(void)
+{
+	return 0x00002a00;
+}
+static inline u32 fifo_fb_timeout_r(void)
+{
+	return 0x00002a04;
+}
+static inline u32 fifo_fb_timeout_period_m(void)
+{
+	return 0x3fffffff << 0;
+}
+static inline u32 fifo_fb_timeout_period_max_f(void)
+{
+	return 0x3fffffff;
+}
+static inline u32 fifo_error_sched_disable_r(void)
+{
+	return 0x0000262c;
+}
+static inline u32 fifo_sched_disable_r(void)
+{
+	return 0x00002630;
+}
+static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
+{
+	return (v & 0x1) << (0 + i*1);
+}
+static inline u32 fifo_sched_disable_runlist_m(u32 i)
+{
+	return 0x1 << (0 + i*1);
+}
+static inline u32 fifo_sched_disable_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_preempt_r(void)
+{
+	return 0x00002634;
+}
+static inline u32 fifo_preempt_pending_true_f(void)
+{
+	return 0x100000;
+}
+static inline u32 fifo_preempt_type_channel_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_preempt_type_tsg_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 fifo_preempt_chid_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 fifo_preempt_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 fifo_trigger_mmu_fault_r(u32 i)
+{
+	return 0x00002a30 + i*4;
+}
+static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
+{
+	return (v & 0x1f) << 0;
+}
+static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
+{
+	return (v & 0x1) << 8;
+}
+static inline u32 fifo_engine_status_r(u32 i)
+{
+	return 0x00002640 + i*8;
+}
+static inline u32 fifo_engine_status__size_1_v(void)
+{
+	return 0x00000009;
+}
+static inline u32 fifo_engine_status_id_v(u32 r)
+{
+	return (r >> 0) & 0xfff;
+}
+static inline u32 fifo_engine_status_id_type_v(u32 r)
+{
+	return (r >> 12) & 0x1;
+}
+static inline u32 fifo_engine_status_id_type_chid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_engine_status_id_type_tsgid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctx_status_v(u32 r)
+{
+	return (r >> 13) & 0x7;
+}
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_engine_status_ctx_status_valid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
+{
+	return 0x00000005;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 fifo_engine_status_next_id_v(u32 r)
+{
+	return (r >> 16) & 0xfff;
+}
+static inline u32 fifo_engine_status_next_id_type_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 fifo_engine_status_next_id_type_chid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_engine_status_faulted_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 fifo_engine_status_faulted_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_engine_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 fifo_engine_status_engine_idle_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_engine_status_engine_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctxsw_v(u32 r)
+{
+	return (r >> 15) & 0x1;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
+{
+	return 0x8000;
+}
+static inline u32 fifo_pbdma_status_r(u32 i)
+{
+	return 0x00003080 + i*4;
+}
+static inline u32 fifo_pbdma_status__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 fifo_pbdma_status_id_v(u32 r)
+{
+	return (r >> 0) & 0xfff;
+}
+static inline u32 fifo_pbdma_status_id_type_v(u32 r)
+{
+	return (r >> 12) & 0x1;
+}
+static inline u32 fifo_pbdma_status_id_type_chid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
+{
+	return (r >> 13) & 0x7;
+}
+static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
+{
+	return 0x00000005;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 fifo_pbdma_status_next_id_v(u32 r)
+{
+	return (r >> 16) & 0xfff;
+}
+static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_pbdma_status_chsw_v(u32 r)
+{
+	return (r >> 15) & 0x1;
+}
+static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_lo_r(void)
+{
+	return 0x00002a70;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
+{
+	return (v & 0xfffff) << 12;
+}
+static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_hi_r(void)
+{
+	return 0x00002a74;
+}
+static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_size_r(void)
+{
+	return 0x00002a78;
+}
+static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
+{
+	return (v & 0x3fff) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
+{
+	return 0x00001200;
+}
+static inline u32 fifo_replay_fault_buffer_get_r(void)
+{
+	return 0x00002a7c;
+}
+static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
+{
+	return (v & 0x3fff) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_put_r(void)
+{
+	return 0x00002a80;
+}
+static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
+{
+	return (v & 0x3fff) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_info_r(void)
+{
+	return 0x00002a84;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
+{
+	return (v & 0x1) << 28;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
+{
+	return 0x00000001;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_flush_gp106.h

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_flush_gp106_h_
+#define _hw_flush_gp106_h_
+
+static inline u32 flush_l2_system_invalidate_r(void)
+{
+	return 0x00070004;
+}
+static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_flush_dirty_r(void)
+{
+	return 0x00070010;
+}
+static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
+{
+	return 0x0;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_clean_comptags_r(void)
+{
+	return 0x0007000c;
+}
+static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
+{
+	return 0x0;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_fb_flush_r(void)
+{
+	return 0x00070000;
+}
+static inline u32 flush_fb_flush_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 flush_fb_flush_pending_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_fb_flush_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 flush_fb_flush_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 flush_fb_flush_outstanding_true_v(void)
+{
+	return 0x00000001;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_fuse_gp106.h

@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fuse_gp106_h_
+#define _hw_fuse_gp106_h_
+
+static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
+{
+	return 0x00021c38 + i*4;
+}
+static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
+{
+	return 0x00021838 + i*4;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
+{
+	return 0x00021944;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
+{
+	return 0x00021948;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
+{
+	return 0x1;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
+{
+	return 0x0;
+}
+static inline u32 fuse_status_opt_fbio_r(void)
+{
+	return 0x00021c14;
+}
+static inline u32 fuse_status_opt_fbio_data_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 fuse_status_opt_fbio_data_m(void)
+{
+	return 0xffff << 0;
+}
+static inline u32 fuse_status_opt_fbio_data_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
+{
+	return 0x00021d70 + i*4;
+}
+static inline u32 fuse_status_opt_fbp_r(void)
+{
+	return 0x00021d38;
+}
+static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
+{
+	return (r >> (0 + i*0)) & 0x1;
+}
+static inline u32 fuse_vin_cal_fuse_rev_r(void)
+{
+	return 0x0002164c;
+}
+static inline u32 fuse_vin_cal_fuse_rev_v(u32 r)
+{
+	return 0x3 & r;
+}
+static inline u32 fuse_vin_cal_gpc0_r(void)
+{
+	return 0x00021650;
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_data_v(u32 r)
+{
+	return ((r & 0xFFFC000) >> 14);
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_frac_size_v(void)
+{
+	return 2;
+}
+static inline u32 fuse_vin_cal_gpc0_slope_data_v(u32 r)
+{
+	return (r & 0x3FFF);
+}
+static inline u32 fuse_vin_cal_gpc0_slope_frac_size_v(void)
+{
+	return 10;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_r(void)
+{
+	return 0x00021654;
+}
+static inline u32 fuse_vin_cal_gpc1_icpt_sign_f(void)
+{
+	return 0x400000;
+}
+static inline u32 fuse_vin_cal_gpc1_slope_sign_f(void)
+{
+	return 0x800;
+}
+static inline u32 fuse_vin_cal_gpc1_icpt_data_v(u32 r)
+{
+	return ((r & 0x3FF000) >> 12);
+}
+static inline u32 fuse_vin_cal_gpc1_icpt_frac_size_v(void)
+{
+	return 2;
+}
+static inline u32 fuse_vin_cal_gpc1_slope_data_v(u32 r)
+{
+	return (r & 0x7FF);
+}
+static inline u32 fuse_vin_cal_gpc1_slope_frac_size_v(void)
+{
+	return 10;
+}
+static inline u32 fuse_vin_cal_gpc2_delta_r(void)
+{
+	return 0x00021658;
+}
+static inline u32 fuse_vin_cal_gpc3_delta_r(void)
+{
+	return 0x0002165c;
+}
+static inline u32 fuse_vin_cal_gpc4_delta_r(void)
+{
+	return 0x00021660;
+}
+static inline u32 fuse_vin_cal_gpc5_delta_r(void)
+{
+	return 0x00021664;
+}
+static inline u32 fuse_vin_cal_shared_delta_r(void)
+{
+	return 0x00021668;
+}
+static inline u32 fuse_vin_cal_sram_delta_r(void)
+{
+	return 0x0002166c;
+}
+static inline u32 fuse_vin_cal_sram_icpt_data_v(u32 r)
+{
+	return ((r & 0x3FF000) >> 12);
+}
+static inline u32 fuse_vin_cal_sram_icpt_frac_size_v(void)
+{
+	return 1;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_gc6_gp106.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gc6_gp106_h_
+#define _hw_gc6_gp106_h_
+static inline u32 gc6_sci_strap_r(void)
+{
+	return 0x00010ebb0;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h

@@ -0,0 +1,553 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ltc_gp106_h_
+#define _hw_ltc_gp106_h_
+
+static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
+{
+	return 0x0014046c;
+}
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+	return 0x00140518;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+	return 0x0017e318;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
+{
+	return 0x1 << 15;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
+{
+	return 0x00140494;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
+{
+	return (r >> 16) & 0x3;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
+{
+	return 0x0017e26c;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
+{
+	return 0x2;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
+{
+	return 0x4;
+}
+static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
+{
+	return 0x0014046c;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
+{
+	return 0x0017e270;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
+{
+	return (v & 0x3ffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
+{
+	return 0x0017e274;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
+{
+	return (v & 0x3ffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
+{
+	return 0x0003ffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
+{
+	return 0x0017e278;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
+{
+	return 0x0000000b;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
+{
+	return (r >> 0) & 0x3ffffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
+{
+	return 0x0017e27c;
+}
+static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
+{
+	return 0x0017e000;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
+{
+	return 0x0017e280;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
+{
+	return (r >> 24) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
+{
+	return (r >> 28) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
+{
+	return 0x0017e3f4;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
+{
+	return 0x0017e2ac;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
+{
+	return (v & 0x1f) << 16;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
+{
+	return 0x0017e338;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
+{
+	return 0x0017e33c + i*4;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
+{
+	return 0x0017e34c;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
+{
+	return 32;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
+{
+	return 0xffffffff << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
+{
+	return 0x0017e2b0;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
+{
+	return 0x0017e214;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
+{
+	return 0x00140214;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
+{
+	return 0x00142214;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+	return 0x0017e20c;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
+{
+	return 0x200;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+	return 0x1 << 20;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
+{
+	return 0x1 << 30;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+	return 0x0014040c;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
+{
+	return 0x0014051c;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
+{
+	return 0xff << 0;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
+{
+	return 0xff << 16;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
+{
+	return (r >> 16) & 0xff;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+	return 0x0017e2a0;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+	return (r >> 8) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+	return 0x300;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+	return (r >> 29) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+	return 0x0017e2a4;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+	return (r >> 8) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+	return 0x300;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+	return (r >> 16) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+	return 0x10000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+	return (r >> 29) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+	return 0x001402a0;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+	return 0x001402a4;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
+{
+	return 0x001422a0;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
+{
+	return 0x001422a4;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
+{
+	return 0x0014058c;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
+{
+	return (r >> 16) & 0x1f;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_mc_gp106.h

@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_mc_gp106_h_
+#define _hw_mc_gp106_h_
+
+static inline u32 mc_boot_0_r(void)
+{
+	return 0x00000000;
+}
+static inline u32 mc_boot_0_architecture_v(u32 r)
+{
+	return (r >> 24) & 0x1f;
+}
+static inline u32 mc_boot_0_implementation_v(u32 r)
+{
+	return (r >> 20) & 0xf;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+	return (r >> 4) & 0xf;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+	return (r >> 0) & 0xf;
+}
+static inline u32 mc_intr_r(u32 i)
+{
+	return 0x00000100 + i*4;
+}
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 mc_intr_replayable_fault_pending_f(void)
+{
+	return 0x200;
+}
+static inline u32 mc_intr_pgraph_pending_f(void)
+{
+	return 0x1000;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 mc_intr_ltc_pending_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 mc_intr_priv_ring_pending_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 mc_intr_pbus_pending_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 mc_intr_en_r(u32 i)
+{
+	return 0x00000140 + i*4;
+}
+static inline u32 mc_intr_en_set_r(u32 i)
+{
+	return 0x00000160 + i*4;
+}
+static inline u32 mc_intr_en_clear_r(u32 i)
+{
+	return 0x00000180 + i*4;
+}
+static inline u32 mc_enable_r(void)
+{
+	return 0x00000200;
+}
+static inline u32 mc_enable_xbar_enabled_f(void)
+{
+	return 0x4;
+}
+static inline u32 mc_enable_l2_enabled_f(void)
+{
+	return 0x8;
+}
+static inline u32 mc_enable_pmedia_s(void)
+{
+	return 1;
+}
+static inline u32 mc_enable_pmedia_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 mc_enable_pmedia_m(void)
+{
+	return 0x1 << 4;
+}
+static inline u32 mc_enable_pmedia_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 mc_enable_priv_ring_enabled_f(void)
+{
+	return 0x20;
+}
+static inline u32 mc_enable_ce0_m(void)
+{
+	return 0x1 << 6;
+}
+static inline u32 mc_enable_pfifo_enabled_f(void)
+{
+	return 0x100;
+}
+static inline u32 mc_enable_pgraph_enabled_f(void)
+{
+	return 0x1000;
+}
+static inline u32 mc_enable_pwr_v(u32 r)
+{
+	return (r >> 13) & 0x1;
+}
+static inline u32 mc_enable_pwr_disabled_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 mc_enable_pwr_enabled_f(void)
+{
+	return 0x2000;
+}
+static inline u32 mc_enable_pfb_enabled_f(void)
+{
+	return 0x100000;
+}
+static inline u32 mc_enable_ce2_m(void)
+{
+	return 0x1 << 21;
+}
+static inline u32 mc_enable_ce2_enabled_f(void)
+{
+	return 0x200000;
+}
+static inline u32 mc_enable_blg_enabled_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 mc_enable_perfmon_enabled_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 mc_enable_hub_enabled_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 mc_intr_ltc_r(void)
+{
+	return 0x000001c0;
+}
+static inline u32 mc_enable_pb_r(void)
+{
+	return 0x00000204;
+}
+static inline u32 mc_enable_pb_0_s(void)
+{
+	return 1;
+}
+static inline u32 mc_enable_pb_0_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 mc_enable_pb_0_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 mc_enable_pb_0_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 mc_enable_pb_0_enabled_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
+{
+	return (v & 0x1) << (0 + i*1);
+}
+static inline u32 mc_elpg_enable_r(void)
+{
+	return 0x0000020c;
+}
+static inline u32 mc_elpg_enable_xbar_enabled_f(void)
+{
+	return 0x4;
+}
+static inline u32 mc_elpg_enable_pfb_enabled_f(void)
+{
+	return 0x100000;
+}
+static inline u32 mc_elpg_enable_hub_enabled_f(void)
+{
+	return 0x20000000;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_pbdma_gp106.h

@@ -0,0 +1,513 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pbdma_gp106_h_
+#define _hw_pbdma_gp106_h_
+
+static inline u32 pbdma_gp_entry1_r(void)
+{
+	return 0x10000004;
+}
+static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 pbdma_gp_entry1_length_f(u32 v)
+{
+	return (v & 0x1fffff) << 10;
+}
+static inline u32 pbdma_gp_entry1_length_v(u32 r)
+{
+	return (r >> 10) & 0x1fffff;
+}
+static inline u32 pbdma_gp_base_r(u32 i)
+{
+	return 0x00040048 + i*8192;
+}
+static inline u32 pbdma_gp_base__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pbdma_gp_base_offset_f(u32 v)
+{
+	return (v & 0x1fffffff) << 3;
+}
+static inline u32 pbdma_gp_base_rsvd_s(void)
+{
+	return 3;
+}
+static inline u32 pbdma_gp_base_hi_r(u32 i)
+{
+	return 0x0004004c + i*8192;
+}
+static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
+{
+	return (v & 0x1f) << 16;
+}
+static inline u32 pbdma_gp_fetch_r(u32 i)
+{
+	return 0x00040050 + i*8192;
+}
+static inline u32 pbdma_gp_get_r(u32 i)
+{
+	return 0x00040014 + i*8192;
+}
+static inline u32 pbdma_gp_put_r(u32 i)
+{
+	return 0x00040000 + i*8192;
+}
+static inline u32 pbdma_pb_fetch_r(u32 i)
+{
+	return 0x00040054 + i*8192;
+}
+static inline u32 pbdma_pb_fetch_hi_r(u32 i)
+{
+	return 0x00040058 + i*8192;
+}
+static inline u32 pbdma_get_r(u32 i)
+{
+	return 0x00040018 + i*8192;
+}
+static inline u32 pbdma_get_hi_r(u32 i)
+{
+	return 0x0004001c + i*8192;
+}
+static inline u32 pbdma_put_r(u32 i)
+{
+	return 0x0004005c + i*8192;
+}
+static inline u32 pbdma_put_hi_r(u32 i)
+{
+	return 0x00040060 + i*8192;
+}
+static inline u32 pbdma_formats_r(u32 i)
+{
+	return 0x0004009c + i*8192;
+}
+static inline u32 pbdma_formats_gp_fermi0_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_formats_pb_fermi1_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_formats_mp_fermi0_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_r(u32 i)
+{
+	return 0x00040084 + i*8192;
+}
+static inline u32 pbdma_pb_header_priv_user_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_method_zero_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_subchannel_zero_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_level_main_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_first_true_f(void)
+{
+	return 0x400000;
+}
+static inline u32 pbdma_pb_header_type_inc_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 pbdma_pb_header_type_non_inc_f(void)
+{
+	return 0x60000000;
+}
+static inline u32 pbdma_hdr_shadow_r(u32 i)
+{
+	return 0x00040118 + i*8192;
+}
+static inline u32 pbdma_subdevice_r(u32 i)
+{
+	return 0x00040094 + i*8192;
+}
+static inline u32 pbdma_subdevice_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 pbdma_subdevice_status_active_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 pbdma_method0_r(u32 i)
+{
+	return 0x000400c0 + i*8192;
+}
+static inline u32 pbdma_method0_fifo_size_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pbdma_method0_addr_f(u32 v)
+{
+	return (v & 0xfff) << 2;
+}
+static inline u32 pbdma_method0_addr_v(u32 r)
+{
+	return (r >> 2) & 0xfff;
+}
+static inline u32 pbdma_method0_subch_v(u32 r)
+{
+	return (r >> 16) & 0x7;
+}
+static inline u32 pbdma_method0_first_true_f(void)
+{
+	return 0x400000;
+}
+static inline u32 pbdma_method0_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 pbdma_method1_r(u32 i)
+{
+	return 0x000400c8 + i*8192;
+}
+static inline u32 pbdma_method2_r(u32 i)
+{
+	return 0x000400d0 + i*8192;
+}
+static inline u32 pbdma_method3_r(u32 i)
+{
+	return 0x000400d8 + i*8192;
+}
+static inline u32 pbdma_data0_r(u32 i)
+{
+	return 0x000400c4 + i*8192;
+}
+static inline u32 pbdma_target_r(u32 i)
+{
+	return 0x000400ac + i*8192;
+}
+static inline u32 pbdma_target_engine_sw_f(void)
+{
+	return 0x1f;
+}
+static inline u32 pbdma_acquire_r(u32 i)
+{
+	return 0x00040030 + i*8192;
+}
+static inline u32 pbdma_acquire_retry_man_2_f(void)
+{
+	return 0x2;
+}
+static inline u32 pbdma_acquire_retry_exp_2_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_f(void)
+{
+	return 0x7800;
+}
+static inline u32 pbdma_acquire_timeout_man_max_f(void)
+{
+	return 0x7fff8000;
+}
+static inline u32 pbdma_acquire_timeout_en_disable_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_status_r(u32 i)
+{
+	return 0x00040100 + i*8192;
+}
+static inline u32 pbdma_channel_r(u32 i)
+{
+	return 0x00040120 + i*8192;
+}
+static inline u32 pbdma_signature_r(u32 i)
+{
+	return 0x00040010 + i*8192;
+}
+static inline u32 pbdma_signature_hw_valid_f(void)
+{
+	return 0xface;
+}
+static inline u32 pbdma_signature_sw_zero_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_userd_r(u32 i)
+{
+	return 0x00040008 + i*8192;
+}
+static inline u32 pbdma_userd_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
+{
+	return 0x2;
+}
+static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
+{
+	return 0x3;
+}
+static inline u32 pbdma_userd_addr_f(u32 v)
+{
+	return (v & 0x7fffff) << 9;
+}
+static inline u32 pbdma_userd_hi_r(u32 i)
+{
+	return 0x0004000c + i*8192;
+}
+static inline u32 pbdma_userd_hi_addr_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 pbdma_config_r(u32 i)
+{
+	return 0x000400f4 + i*8192;
+}
+static inline u32 pbdma_config_auth_level_privileged_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_hce_ctrl_r(u32 i)
+{
+	return 0x000400e4 + i*8192;
+}
+static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
+{
+	return 0x20;
+}
+static inline u32 pbdma_intr_0_r(u32 i)
+{
+	return 0x00040108 + i*8192;
+}
+static inline u32 pbdma_intr_0_memreq_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 pbdma_intr_0_memreq_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
+{
+	return 0x4;
+}
+static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
+{
+	return 0x8;
+}
+static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
+{
+	return 0x10;
+}
+static inline u32 pbdma_intr_0_memflush_pending_f(void)
+{
+	return 0x20;
+}
+static inline u32 pbdma_intr_0_memop_pending_f(void)
+{
+	return 0x40;
+}
+static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
+{
+	return 0x80;
+}
+static inline u32 pbdma_intr_0_lbreq_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
+{
+	return 0x200;
+}
+static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
+{
+	return 0x400;
+}
+static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
+{
+	return 0x800;
+}
+static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
+{
+	return 0x1000;
+}
+static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
+{
+	return 0x2000;
+}
+static inline u32 pbdma_intr_0_gpptr_pending_f(void)
+{
+	return 0x4000;
+}
+static inline u32 pbdma_intr_0_gpentry_pending_f(void)
+{
+	return 0x8000;
+}
+static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
+{
+	return 0x10000;
+}
+static inline u32 pbdma_intr_0_pbptr_pending_f(void)
+{
+	return 0x20000;
+}
+static inline u32 pbdma_intr_0_pbentry_pending_f(void)
+{
+	return 0x40000;
+}
+static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
+{
+	return 0x80000;
+}
+static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
+{
+	return 0x100000;
+}
+static inline u32 pbdma_intr_0_method_pending_f(void)
+{
+	return 0x200000;
+}
+static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
+{
+	return 0x400000;
+}
+static inline u32 pbdma_intr_0_device_pending_f(void)
+{
+	return 0x800000;
+}
+static inline u32 pbdma_intr_0_semaphore_pending_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 pbdma_intr_0_acquire_pending_f(void)
+{
+	return 0x4000000;
+}
+static inline u32 pbdma_intr_0_pri_pending_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 pbdma_intr_0_pbseg_pending_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 pbdma_intr_0_signature_pending_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+	return 0x00040148 + i*8192;
+}
+static inline u32 pbdma_intr_en_0_r(u32 i)
+{
+	return 0x0004010c + i*8192;
+}
+static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_intr_en_1_r(u32 i)
+{
+	return 0x0004014c + i*8192;
+}
+static inline u32 pbdma_intr_stall_r(u32 i)
+{
+	return 0x0004013c + i*8192;
+}
+static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_udma_nop_r(void)
+{
+	return 0x00000008;
+}
+static inline u32 pbdma_runlist_timeslice_r(u32 i)
+{
+	return 0x000400f8 + i*8192;
+}
+static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
+{
+	return 0x80;
+}
+static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
+{
+	return 0x3000;
+}
+static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
+{
+	return 0x10000000;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_perf_gp106.h

@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_perf_gp106_h_
+#define _hw_perf_gp106_h_
+
+static inline u32 perf_pmasys_control_r(void)
+{
+	return 0x001b4000;
+}
+static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
+{
+	return 0x10;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
+{
+	return (r >> 5) & 0x1;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
+{
+	return 0x20;
+}
+static inline u32 perf_pmasys_mem_block_r(void)
+{
+	return 0x001b4070;
+}
+static inline u32 perf_pmasys_mem_block_base_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 perf_pmasys_mem_block_target_f(u32 v)
+{
+	return (v & 0x3) << 28;
+}
+static inline u32 perf_pmasys_mem_block_target_v(u32 r)
+{
+	return (r >> 28) & 0x3;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
+{
+	return 0x0;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 perf_pmasys_outbase_r(void)
+{
+	return 0x001b4074;
+}
+static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
+{
+	return (v & 0x7ffffff) << 5;
+}
+static inline u32 perf_pmasys_outbaseupper_r(void)
+{
+	return 0x001b4078;
+}
+static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 perf_pmasys_outsize_r(void)
+{
+	return 0x001b407c;
+}
+static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
+{
+	return (v & 0x7ffffff) << 5;
+}
+static inline u32 perf_pmasys_mem_bytes_r(void)
+{
+	return 0x001b4084;
+}
+static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 perf_pmasys_mem_bump_r(void)
+{
+	return 0x001b4088;
+}
+static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 perf_pmasys_enginestatus_r(void)
+{
+	return 0x001b40a4;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
+{
+	return 0x10;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_pri_ringmaster_gp106.h

@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringmaster_gp106_h_
+#define _hw_pri_ringmaster_gp106_h_
+
+static inline u32 pri_ringmaster_command_r(void)
+{
+	return 0x0012004c;
+}
+static inline u32 pri_ringmaster_command_cmd_m(void)
+{
+	return 0x3f << 0;
+}
+static inline u32 pri_ringmaster_command_cmd_v(u32 r)
+{
+	return (r >> 0) & 0x3f;
+}
+static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
+{
+	return 0x1;
+}
+static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
+{
+	return 0x2;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
+{
+	return 0x3;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
+{
+	return 0x0;
+}
+static inline u32 pri_ringmaster_command_data_r(void)
+{
+	return 0x00120048;
+}
+static inline u32 pri_ringmaster_start_results_r(void)
+{
+	return 0x00120050;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 pri_ringmaster_intr_status0_r(void)
+{
+	return 0x00120058;
+}
+static inline u32 pri_ringmaster_intr_status1_r(void)
+{
+	return 0x0012005c;
+}
+static inline u32 pri_ringmaster_global_ctl_r(void)
+{
+	return 0x00120060;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
+{
+	return 0x1;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
+{
+	return 0x0;
+}
+static inline u32 pri_ringmaster_enum_fbp_r(void)
+{
+	return 0x00120074;
+}
+static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 pri_ringmaster_enum_gpc_r(void)
+{
+	return 0x00120078;
+}
+static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 pri_ringmaster_enum_ltc_r(void)
+{
+	return 0x0012006c;
+}
+static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_pri_ringstation_sys_gp106.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_sys_gp106_h_
+#define _hw_pri_ringstation_sys_gp106_h_
+
+static inline u32 pri_ringstation_sys_master_config_r(u32 i)
+{
+	return 0x00122300 + i*4;
+}
+static inline u32 pri_ringstation_sys_decode_config_r(void)
+{
+	return 0x00122204;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
+{
+	return 0x7 << 0;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
+{
+	return 0x1;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_proj_gp106.h

@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_proj_gp106_h_
+#define _hw_proj_gp106_h_
+
+static inline u32 proj_gpc_base_v(void)
+{
+	return 0x00500000;
+}
+static inline u32 proj_gpc_shared_base_v(void)
+{
+	return 0x00418000;
+}
+static inline u32 proj_gpc_stride_v(void)
+{
+	return 0x00008000;
+}
+static inline u32 proj_ltc_stride_v(void)
+{
+	return 0x00002000;
+}
+static inline u32 proj_lts_stride_v(void)
+{
+	return 0x00000200;
+}
+static inline u32 proj_fbpa_base_v(void)
+{
+	return 0x00900000;
+}
+static inline u32 proj_fbpa_shared_base_v(void)
+{
+	return 0x009a0000;
+}
+static inline u32 proj_fbpa_stride_v(void)
+{
+	return 0x00004000;
+}
+static inline u32 proj_ppc_in_gpc_base_v(void)
+{
+	return 0x00003000;
+}
+static inline u32 proj_ppc_in_gpc_shared_base_v(void)
+{
+	return 0x00003e00;
+}
+static inline u32 proj_ppc_in_gpc_stride_v(void)
+{
+	return 0x00000200;
+}
+static inline u32 proj_rop_base_v(void)
+{
+	return 0x00410000;
+}
+static inline u32 proj_rop_shared_base_v(void)
+{
+	return 0x00408800;
+}
+static inline u32 proj_rop_stride_v(void)
+{
+	return 0x00000400;
+}
+static inline u32 proj_tpc_in_gpc_base_v(void)
+{
+	return 0x00004000;
+}
+static inline u32 proj_tpc_in_gpc_stride_v(void)
+{
+	return 0x00000800;
+}
+static inline u32 proj_tpc_in_gpc_shared_base_v(void)
+{
+	return 0x00001800;
+}
+static inline u32 proj_host_num_engines_v(void)
+{
+	return 0x00000009;
+}
+static inline u32 proj_host_num_pbdma_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
+{
+	return 0x00000005;
+}
+static inline u32 proj_scal_litter_num_fbps_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_gpcs_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 proj_scal_litter_num_zcull_banks_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 proj_scal_max_gpcs_v(void)
+{
+	return 0x00000020;
+}
+static inline u32 proj_scal_max_tpc_per_gpc_v(void)
+{
+	return 0x00000008;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_psec_gp106.h

@@ -0,0 +1,609 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_psec_gp106_h_
+#define _hw_psec_gp106_h_
+
+static inline u32 psec_falcon_irqsset_r(void)
+{
+	return 0x00087000;
+}
+static inline u32 psec_falcon_irqsset_swgen0_set_f(void)
+{
+	return 0x40;
+}
+static inline u32 psec_falcon_irqsclr_r(void)
+{
+	return 0x00087004;
+}
+static inline u32 psec_falcon_irqstat_r(void)
+{
+	return 0x00087008;
+}
+static inline u32 psec_falcon_irqstat_halt_true_f(void)
+{
+	return 0x10;
+}
+static inline u32 psec_falcon_irqstat_exterr_true_f(void)
+{
+	return 0x20;
+}
+static inline u32 psec_falcon_irqstat_swgen0_true_f(void)
+{
+	return 0x40;
+}
+static inline u32 psec_falcon_irqmode_r(void)
+{
+	return 0x0008700c;
+}
+static inline u32 psec_falcon_irqmset_r(void)
+{
+	return 0x00087010;
+}
+static inline u32 psec_falcon_irqmset_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 psec_falcon_irqmset_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_irqmset_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 psec_falcon_irqmset_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 psec_falcon_irqmset_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_irqmset_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 psec_falcon_irqmset_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 psec_falcon_irqmset_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 psec_falcon_irqmclr_r(void)
+{
+	return 0x00087014;
+}
+static inline u32 psec_falcon_irqmclr_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 psec_falcon_irqmclr_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_irqmclr_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 psec_falcon_irqmclr_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 psec_falcon_irqmclr_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_irqmclr_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 psec_falcon_irqmclr_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 psec_falcon_irqmclr_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 psec_falcon_irqmclr_ext_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 psec_falcon_irqmask_r(void)
+{
+	return 0x00087018;
+}
+static inline u32 psec_falcon_irqdest_r(void)
+{
+	return 0x0008701c;
+}
+static inline u32 psec_falcon_irqdest_host_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 psec_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_irqdest_host_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 psec_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 psec_falcon_irqdest_host_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_irqdest_host_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 psec_falcon_irqdest_host_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 psec_falcon_irqdest_host_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 psec_falcon_irqdest_host_ext_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 psec_falcon_irqdest_target_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 16;
+}
+static inline u32 psec_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 17;
+}
+static inline u32 psec_falcon_irqdest_target_mthd_f(u32 v)
+{
+	return (v & 0x1) << 18;
+}
+static inline u32 psec_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 19;
+}
+static inline u32 psec_falcon_irqdest_target_halt_f(u32 v)
+{
+	return (v & 0x1) << 20;
+}
+static inline u32 psec_falcon_irqdest_target_exterr_f(u32 v)
+{
+	return (v & 0x1) << 21;
+}
+static inline u32 psec_falcon_irqdest_target_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 22;
+}
+static inline u32 psec_falcon_irqdest_target_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 23;
+}
+static inline u32 psec_falcon_irqdest_target_ext_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+static inline u32 psec_falcon_curctx_r(void)
+{
+	return 0x00087050;
+}
+static inline u32 psec_falcon_nxtctx_r(void)
+{
+	return 0x00087054;
+}
+static inline u32 psec_falcon_mailbox0_r(void)
+{
+	return 0x00087040;
+}
+static inline u32 psec_falcon_mailbox1_r(void)
+{
+	return 0x00087044;
+}
+static inline u32 psec_falcon_itfen_r(void)
+{
+	return 0x00087048;
+}
+static inline u32 psec_falcon_itfen_ctxen_enable_f(void)
+{
+	return 0x1;
+}
+static inline u32 psec_falcon_idlestate_r(void)
+{
+	return 0x0008704c;
+}
+static inline u32 psec_falcon_idlestate_falcon_busy_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 psec_falcon_idlestate_ext_busy_v(u32 r)
+{
+	return (r >> 1) & 0x7fff;
+}
+static inline u32 psec_falcon_os_r(void)
+{
+	return 0x00087080;
+}
+static inline u32 psec_falcon_engctl_r(void)
+{
+	return 0x000870a4;
+}
+static inline u32 psec_falcon_cpuctl_r(void)
+{
+	return 0x00087100;
+}
+static inline u32 psec_falcon_cpuctl_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_m(void)
+{
+	return 0x1 << 4;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+	return 0x1 << 6;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+	return (r >> 6) & 0x1;
+}
+static inline u32 psec_falcon_cpuctl_alias_r(void)
+{
+	return 0x00087130;
+}
+static inline u32 psec_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_imemc_r(u32 i)
+{
+	return 0x00087180 + i*16;
+}
+static inline u32 psec_falcon_imemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 psec_falcon_imemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 psec_falcon_imemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 psec_falcon_imemd_r(u32 i)
+{
+	return 0x00087184 + i*16;
+}
+static inline u32 psec_falcon_imemt_r(u32 i)
+{
+	return 0x00087188 + i*16;
+}
+static inline u32 psec_falcon_sctl_r(void)
+{
+	return 0x00087240;
+}
+static inline u32 psec_falcon_mmu_phys_sec_r(void)
+{
+	return 0x00100ce4;
+}
+static inline u32 psec_falcon_bootvec_r(void)
+{
+	return 0x00087104;
+}
+static inline u32 psec_falcon_bootvec_vec_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 psec_falcon_dmactl_r(void)
+{
+	return 0x0008710c;
+}
+static inline u32 psec_falcon_dmactl_dmem_scrubbing_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 psec_falcon_dmactl_imem_scrubbing_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 psec_falcon_dmactl_require_ctx_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 psec_falcon_hwcfg_r(void)
+{
+	return 0x00087108;
+}
+static inline u32 psec_falcon_hwcfg_imem_size_v(u32 r)
+{
+	return (r >> 0) & 0x1ff;
+}
+static inline u32 psec_falcon_hwcfg_dmem_size_v(u32 r)
+{
+	return (r >> 9) & 0x1ff;
+}
+static inline u32 psec_falcon_dmatrfbase_r(void)
+{
+	return 0x00087110;
+}
+static inline u32 psec_falcon_dmatrfbase1_r(void)
+{
+	return 0x00087128;
+}
+static inline u32 psec_falcon_dmatrfmoffs_r(void)
+{
+	return 0x00087114;
+}
+static inline u32 psec_falcon_dmatrfcmd_r(void)
+{
+	return 0x00087118;
+}
+static inline u32 psec_falcon_dmatrfcmd_imem_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_dmatrfcmd_write_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 psec_falcon_dmatrfcmd_size_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 psec_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+	return (v & 0x7) << 12;
+}
+static inline u32 psec_falcon_dmatrffboffs_r(void)
+{
+	return 0x0008711c;
+}
+static inline u32 psec_falcon_exterraddr_r(void)
+{
+	return 0x00087168;
+}
+static inline u32 psec_falcon_exterrstat_r(void)
+{
+	return 0x0008716c;
+}
+static inline u32 psec_falcon_exterrstat_valid_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 psec_falcon_exterrstat_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 psec_falcon_exterrstat_valid_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_r(void)
+{
+	return 0x00087200;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_s(void)
+{
+	return 4;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_m(void)
+{
+	return 0xf << 0;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_v(u32 r)
+{
+	return (r >> 0) & 0xf;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_rreg_f(void)
+{
+	return 0x8;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_rstat_f(void)
+{
+	return 0xe;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_idx_f(u32 v)
+{
+	return (v & 0x1f) << 8;
+}
+static inline u32 psec_sec2_falcon_icd_rdata_r(void)
+{
+	return 0x0008720c;
+}
+static inline u32 psec_falcon_dmemc_r(u32 i)
+{
+	return 0x000871c0 + i*8;
+}
+static inline u32 psec_falcon_dmemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 psec_falcon_dmemc_offs_m(void)
+{
+	return 0x3f << 2;
+}
+static inline u32 psec_falcon_dmemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 psec_falcon_dmemc_blk_m(void)
+{
+	return 0xff << 8;
+}
+static inline u32 psec_falcon_dmemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 psec_falcon_dmemc_aincr_f(u32 v)
+{
+	return (v & 0x1) << 25;
+}
+static inline u32 psec_falcon_dmemd_r(u32 i)
+{
+	return 0x000871c4 + i*8;
+}
+static inline u32 psec_falcon_debug1_r(void)
+{
+	return 0x00087090;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_s(void)
+{
+	return 1;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+	return (v & 0x1) << 16;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_m(void)
+{
+	return 0x1 << 16;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+	return (r >> 16) & 0x1;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_init_f(void)
+{
+	return 0x0;
+}
+static inline u32 psec_fbif_transcfg_r(u32 i)
+{
+	return 0x00087600 + i*4;
+}
+static inline u32 psec_fbif_transcfg_target_local_fb_f(void)
+{
+	return 0x0;
+}
+static inline u32 psec_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+	return 0x1;
+}
+static inline u32 psec_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+	return 0x2;
+}
+static inline u32 psec_fbif_transcfg_mem_type_s(void)
+{
+	return 1;
+}
+static inline u32 psec_fbif_transcfg_mem_type_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 psec_fbif_transcfg_mem_type_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 psec_fbif_transcfg_mem_type_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 psec_fbif_transcfg_mem_type_virtual_f(void)
+{
+	return 0x0;
+}
+static inline u32 psec_fbif_transcfg_mem_type_physical_f(void)
+{
+	return 0x4;
+}
+static inline u32 psec_falcon_engine_r(void)
+{
+	return 0x000873c0;
+}
+static inline u32 psec_falcon_engine_reset_true_f(void)
+{
+	return 0x1;
+}
+static inline u32 psec_falcon_engine_reset_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 psec_fbif_ctl_r(void)
+{
+	return 0x00087624;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_init_f(void)
+{
+	return 0x0;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_disallow_f(void)
+{
+	return 0x0;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_allow_f(void)
+{
+	return 0x80;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_pwr_gp106.h

@@ -0,0 +1,841 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pwr_gp106_h_
+#define _hw_pwr_gp106_h_
+
+static inline u32 pwr_falcon_irqsset_r(void)
+{
+	return 0x0010a000;
+}
+static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
+{
+	return 0x40;
+}
+static inline u32 pwr_falcon_irqsclr_r(void)
+{
+	return 0x0010a004;
+}
+static inline u32 pwr_falcon_irqstat_r(void)
+{
+	return 0x0010a008;
+}
+static inline u32 pwr_falcon_irqstat_halt_true_f(void)
+{
+	return 0x10;
+}
+static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
+{
+	return 0x20;
+}
+static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
+{
+	return 0x40;
+}
+static inline u32 pwr_falcon_irqmode_r(void)
+{
+	return 0x0010a00c;
+}
+static inline u32 pwr_falcon_irqmset_r(void)
+{
+	return 0x0010a010;
+}
+static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqmclr_r(void)
+{
+	return 0x0010a014;
+}
+static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_irqmask_r(void)
+{
+	return 0x0010a018;
+}
+static inline u32 pwr_falcon_irqdest_r(void)
+{
+	return 0x0010a01c;
+}
+static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 16;
+}
+static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 17;
+}
+static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
+{
+	return (v & 0x1) << 18;
+}
+static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 19;
+}
+static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
+{
+	return (v & 0x1) << 20;
+}
+static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
+{
+	return (v & 0x1) << 21;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 22;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 23;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+static inline u32 pwr_falcon_curctx_r(void)
+{
+	return 0x0010a050;
+}
+static inline u32 pwr_falcon_nxtctx_r(void)
+{
+	return 0x0010a054;
+}
+static inline u32 pwr_falcon_mailbox0_r(void)
+{
+	return 0x0010a040;
+}
+static inline u32 pwr_falcon_mailbox1_r(void)
+{
+	return 0x0010a044;
+}
+static inline u32 pwr_falcon_itfen_r(void)
+{
+	return 0x0010a048;
+}
+static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
+{
+	return 0x1;
+}
+static inline u32 pwr_falcon_idlestate_r(void)
+{
+	return 0x0010a04c;
+}
+static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
+{
+	return (r >> 1) & 0x7fff;
+}
+static inline u32 pwr_falcon_os_r(void)
+{
+	return 0x0010a080;
+}
+static inline u32 pwr_falcon_engctl_r(void)
+{
+	return 0x0010a0a4;
+}
+static inline u32 pwr_falcon_cpuctl_r(void)
+{
+	return 0x0010a100;
+}
+static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+	return 0x1 << 4;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+	return 0x1 << 6;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+	return (r >> 6) & 0x1;
+}
+static inline u32 pwr_falcon_cpuctl_alias_r(void)
+{
+	return 0x0010a130;
+}
+static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_pmu_scpctl_stat_r(void)
+{
+	return 0x0010ac08;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
+{
+	return (v & 0x1) << 20;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
+{
+	return 0x1 << 20;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
+{
+	return (r >> 20) & 0x1;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+	return 0x0010a180 + i*16;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+	return 0x0010a184 + i*16;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+	return 0x0010a188 + i*16;
+}
+static inline u32 pwr_falcon_sctl_r(void)
+{
+	return 0x0010a240;
+}
+static inline u32 pwr_falcon_mmu_phys_sec_r(void)
+{
+	return 0x00100ce4;
+}
+static inline u32 pwr_falcon_bootvec_r(void)
+{
+	return 0x0010a104;
+}
+static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_falcon_dmactl_r(void)
+{
+	return 0x0010a10c;
+}
+static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_hwcfg_r(void)
+{
+	return 0x0010a108;
+}
+static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
+{
+	return (r >> 0) & 0x1ff;
+}
+static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
+{
+	return (r >> 9) & 0x1ff;
+}
+static inline u32 pwr_falcon_dmatrfbase_r(void)
+{
+	return 0x0010a110;
+}
+static inline u32 pwr_falcon_dmatrfbase1_r(void)
+{
+	return 0x0010a128;
+}
+static inline u32 pwr_falcon_dmatrfmoffs_r(void)
+{
+	return 0x0010a114;
+}
+static inline u32 pwr_falcon_dmatrfcmd_r(void)
+{
+	return 0x0010a118;
+}
+static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+	return (v & 0x7) << 12;
+}
+static inline u32 pwr_falcon_dmatrffboffs_r(void)
+{
+	return 0x0010a11c;
+}
+static inline u32 pwr_falcon_exterraddr_r(void)
+{
+	return 0x0010a168;
+}
+static inline u32 pwr_falcon_exterrstat_r(void)
+{
+	return 0x0010a16c;
+}
+static inline u32 pwr_falcon_exterrstat_valid_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
+{
+	return 0x0010a200;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
+{
+	return 4;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
+{
+	return 0xf << 0;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
+{
+	return (r >> 0) & 0xf;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
+{
+	return 0x8;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
+{
+	return 0xe;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
+{
+	return (v & 0x1f) << 8;
+}
+static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
+{
+	return 0x0010a20c;
+}
+static inline u32 pwr_falcon_dmemc_r(u32 i)
+{
+	return 0x0010a1c0 + i*8;
+}
+static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 pwr_falcon_dmemc_offs_m(void)
+{
+	return 0x3f << 2;
+}
+static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_dmemc_blk_m(void)
+{
+	return 0xff << 8;
+}
+static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
+{
+	return (v & 0x1) << 25;
+}
+static inline u32 pwr_falcon_dmemd_r(u32 i)
+{
+	return 0x0010a1c4 + i*8;
+}
+static inline u32 pwr_pmu_new_instblk_r(void)
+{
+	return 0x0010a480;
+}
+static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
+{
+	return (v & 0x1) << 30;
+}
+static inline u32 pwr_pmu_mutex_id_r(void)
+{
+	return 0x0010a488;
+}
+static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 pwr_pmu_mutex_id_value_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
+{
+	return 0x000000ff;
+}
+static inline u32 pwr_pmu_mutex_id_release_r(void)
+{
+	return 0x0010a48c;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_m(void)
+{
+	return 0xff << 0;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_pmu_mutex_r(u32 i)
+{
+	return 0x0010a580 + i*4;
+}
+static inline u32 pwr_pmu_mutex__size_1_v(void)
+{
+	return 0x00000010;
+}
+static inline u32 pwr_pmu_mutex_value_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 pwr_pmu_mutex_value_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_pmu_queue_head_r(u32 i)
+{
+	return 0x0010a4a0 + i*4;
+}
+static inline u32 pwr_pmu_queue_head__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pwr_pmu_queue_head_address_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_queue_head_address_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_queue_tail_r(u32 i)
+{
+	return 0x0010a4b0 + i*4;
+}
+static inline u32 pwr_pmu_queue_tail__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_msgq_head_r(void)
+{
+	return 0x0010a4c8;
+}
+static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_msgq_tail_r(void)
+{
+	return 0x0010a4cc;
+}
+static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_idle_mask_r(u32 i)
+{
+	return 0x0010a504 + i*16;
+}
+static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
+{
+	return 0x1;
+}
+static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
+{
+	return 0x200000;
+}
+static inline u32 pwr_pmu_idle_count_r(u32 i)
+{
+	return 0x0010a508 + i*16;
+}
+static inline u32 pwr_pmu_idle_count_value_f(u32 v)
+{
+	return (v & 0x7fffffff) << 0;
+}
+static inline u32 pwr_pmu_idle_count_value_v(u32 r)
+{
+	return (r >> 0) & 0x7fffffff;
+}
+static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
+{
+	return 0x0010a50c + i*16;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
+{
+	return 0x2;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
+{
+	return 0x3;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
+{
+	return 0x0010a9f0 + i*8;
+}
+static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
+{
+	return 0x0010a9f4 + i*8;
+}
+static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
+{
+	return 0x0010aa30 + i*8;
+}
+static inline u32 pwr_pmu_debug_r(u32 i)
+{
+	return 0x0010a5c0 + i*4;
+}
+static inline u32 pwr_pmu_debug__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pwr_pmu_mailbox_r(u32 i)
+{
+	return 0x0010a450 + i*4;
+}
+static inline u32 pwr_pmu_mailbox__size_1_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 pwr_pmu_bar0_addr_r(void)
+{
+	return 0x0010a7a0;
+}
+static inline u32 pwr_pmu_bar0_data_r(void)
+{
+	return 0x0010a7a4;
+}
+static inline u32 pwr_pmu_bar0_ctl_r(void)
+{
+	return 0x0010a7ac;
+}
+static inline u32 pwr_pmu_bar0_timeout_r(void)
+{
+	return 0x0010a7a8;
+}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+	return 0x0010a988;
+}
+static inline u32 pwr_pmu_bar0_error_status_r(void)
+{
+	return 0x0010a7b0;
+}
+static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
+{
+	return 0x0010a6c0 + i*4;
+}
+static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
+{
+	return 0x0010a6e8 + i*4;
+}
+static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
+{
+	return 0x0010a710 + i*4;
+}
+static inline u32 pwr_pmu_pg_intren_r(u32 i)
+{
+	return 0x0010a760 + i*4;
+}
+static inline u32 pwr_fbif_transcfg_r(u32 i)
+{
+	return 0x0010ae00 + i*4;
+}
+static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+	return 0x1;
+}
+static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+	return 0x2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_s(void)
+{
+	return 1;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
+{
+	return 0x4;
+}
+static inline u32 pwr_falcon_engine_r(void)
+{
+	return 0x0010a3c0;
+}
+static inline u32 pwr_falcon_engine_reset_true_f(void)
+{
+	return 0x1;
+}
+static inline u32 pwr_falcon_engine_reset_false_f(void)
+{
+	return 0x0;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_ram_gp106.h

@@ -0,0 +1,481 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ram_gp106_h_
+#define _hw_ram_gp106_h_
+
+static inline u32 ram_in_ramfc_s(void)
+{
+	return 4096;
+}
+static inline u32 ram_in_ramfc_w(void)
+{
+	return 0;
+}
+static inline u32 ram_in_page_dir_base_target_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 ram_in_page_dir_base_target_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
+{
+	return 0x2;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
+{
+	return 0x3;
+}
+static inline u32 ram_in_page_dir_base_vol_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_page_dir_base_vol_true_f(void)
+{
+	return 0x4;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
+{
+	return 0x1 << 4;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
+{
+	return 0x10;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
+{
+	return 0x1 << 5;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
+{
+	return 0x20;
+}
+static inline u32 ram_in_big_page_size_f(u32 v)
+{
+	return (v & 0x1) << 11;
+}
+static inline u32 ram_in_big_page_size_m(void)
+{
+	return 0x1 << 11;
+}
+static inline u32 ram_in_big_page_size_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_big_page_size_128kb_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_big_page_size_64kb_f(void)
+{
+	return 0x800;
+}
+static inline u32 ram_in_page_dir_base_lo_f(u32 v)
+{
+	return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_page_dir_base_lo_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_page_dir_base_hi_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 ram_in_page_dir_base_hi_w(void)
+{
+	return 129;
+}
+static inline u32 ram_in_adr_limit_lo_f(u32 v)
+{
+	return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_adr_limit_lo_w(void)
+{
+	return 130;
+}
+static inline u32 ram_in_adr_limit_hi_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 ram_in_adr_limit_hi_w(void)
+{
+	return 131;
+}
+static inline u32 ram_in_engine_cs_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_engine_cs_wfi_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ram_in_engine_cs_wfi_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_engine_cs_fg_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ram_in_engine_cs_fg_f(void)
+{
+	return 0x8;
+}
+static inline u32 ram_in_gr_cs_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_gr_cs_wfi_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_gr_wfi_target_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_gr_wfi_mode_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
+{
+	return 0x4;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
+{
+	return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
+{
+	return 133;
+}
+static inline u32 ram_in_base_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 ram_in_alloc_size_v(void)
+{
+	return 0x00001000;
+}
+static inline u32 ram_fc_size_val_v(void)
+{
+	return 0x00000200;
+}
+static inline u32 ram_fc_gp_put_w(void)
+{
+	return 0;
+}
+static inline u32 ram_fc_userd_w(void)
+{
+	return 2;
+}
+static inline u32 ram_fc_userd_hi_w(void)
+{
+	return 3;
+}
+static inline u32 ram_fc_signature_w(void)
+{
+	return 4;
+}
+static inline u32 ram_fc_gp_get_w(void)
+{
+	return 5;
+}
+static inline u32 ram_fc_pb_get_w(void)
+{
+	return 6;
+}
+static inline u32 ram_fc_pb_get_hi_w(void)
+{
+	return 7;
+}
+static inline u32 ram_fc_pb_top_level_get_w(void)
+{
+	return 8;
+}
+static inline u32 ram_fc_pb_top_level_get_hi_w(void)
+{
+	return 9;
+}
+static inline u32 ram_fc_acquire_w(void)
+{
+	return 12;
+}
+static inline u32 ram_fc_semaphorea_w(void)
+{
+	return 14;
+}
+static inline u32 ram_fc_semaphoreb_w(void)
+{
+	return 15;
+}
+static inline u32 ram_fc_semaphorec_w(void)
+{
+	return 16;
+}
+static inline u32 ram_fc_semaphored_w(void)
+{
+	return 17;
+}
+static inline u32 ram_fc_gp_base_w(void)
+{
+	return 18;
+}
+static inline u32 ram_fc_gp_base_hi_w(void)
+{
+	return 19;
+}
+static inline u32 ram_fc_gp_fetch_w(void)
+{
+	return 20;
+}
+static inline u32 ram_fc_pb_fetch_w(void)
+{
+	return 21;
+}
+static inline u32 ram_fc_pb_fetch_hi_w(void)
+{
+	return 22;
+}
+static inline u32 ram_fc_pb_put_w(void)
+{
+	return 23;
+}
+static inline u32 ram_fc_pb_put_hi_w(void)
+{
+	return 24;
+}
+static inline u32 ram_fc_pb_header_w(void)
+{
+	return 33;
+}
+static inline u32 ram_fc_pb_count_w(void)
+{
+	return 34;
+}
+static inline u32 ram_fc_subdevice_w(void)
+{
+	return 37;
+}
+static inline u32 ram_fc_formats_w(void)
+{
+	return 39;
+}
+static inline u32 ram_fc_target_w(void)
+{
+	return 43;
+}
+static inline u32 ram_fc_hce_ctrl_w(void)
+{
+	return 57;
+}
+static inline u32 ram_fc_chid_w(void)
+{
+	return 58;
+}
+static inline u32 ram_fc_chid_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_fc_chid_id_w(void)
+{
+	return 0;
+}
+static inline u32 ram_fc_config_w(void)
+{
+	return 61;
+}
+static inline u32 ram_fc_runlist_timeslice_w(void)
+{
+	return 62;
+}
+static inline u32 ram_userd_base_shift_v(void)
+{
+	return 0x00000009;
+}
+static inline u32 ram_userd_chan_size_v(void)
+{
+	return 0x00000200;
+}
+static inline u32 ram_userd_put_w(void)
+{
+	return 16;
+}
+static inline u32 ram_userd_get_w(void)
+{
+	return 17;
+}
+static inline u32 ram_userd_ref_w(void)
+{
+	return 18;
+}
+static inline u32 ram_userd_put_hi_w(void)
+{
+	return 19;
+}
+static inline u32 ram_userd_ref_threshold_w(void)
+{
+	return 20;
+}
+static inline u32 ram_userd_top_level_get_w(void)
+{
+	return 22;
+}
+static inline u32 ram_userd_top_level_get_hi_w(void)
+{
+	return 23;
+}
+static inline u32 ram_userd_get_hi_w(void)
+{
+	return 24;
+}
+static inline u32 ram_userd_gp_get_w(void)
+{
+	return 34;
+}
+static inline u32 ram_userd_gp_put_w(void)
+{
+	return 35;
+}
+static inline u32 ram_userd_gp_top_level_get_w(void)
+{
+	return 22;
+}
+static inline u32 ram_userd_gp_top_level_get_hi_w(void)
+{
+	return 23;
+}
+static inline u32 ram_rl_entry_size_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+	return (v & 0x1) << 13;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+	return 0x2000;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+	return (v & 0xf) << 14;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+	return 0xc000;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+	return (v & 0xff) << 18;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+	return (v & 0x3f) << 26;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_therm_gp106.h

@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_therm_gp106_h_
+#define _hw_therm_gp106_h_
+
+static inline u32 therm_temp_sensor_tsense_r(void)
+{
+	return 0x00020460;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_f(u32 v)
+{
+	return (v & 0x3fff) << 3;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_m(void)
+{
+	return 0x3fff << 3;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_v(u32 r)
+{
+	return (r >> 3) & 0x3fff;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_min_v(void)
+{
+	return 0x00003b00;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_max_v(void)
+{
+	return 0x000010e0;
+}
+static inline u32 therm_temp_sensor_tsense_state_f(u32 v)
+{
+	return (v & 0x3) << 29;
+}
+static inline u32 therm_temp_sensor_tsense_state_m(void)
+{
+	return 0x3 << 29;
+}
+static inline u32 therm_temp_sensor_tsense_state_v(u32 r)
+{
+	return (r >> 29) & 0x3;
+}
+static inline u32 therm_temp_sensor_tsense_state_valid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 therm_temp_sensor_tsense_state_shadow_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 therm_gate_ctrl_r(u32 i)
+{
+	return 0x00020200 + i*4;
+}
+static inline u32 therm_gate_ctrl_eng_clk_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
+{
+	return 0x0;
+}
+static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
+{
+	return 0x1;
+}
+static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
+{
+	return 0x2;
+}
+static inline u32 therm_gate_ctrl_blk_clk_m(void)
+{
+	return 0x3 << 2;
+}
+static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
+{
+	return 0x0;
+}
+static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
+{
+	return 0x4;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
+{
+	return (v & 0x1f) << 8;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
+{
+	return 0x1f << 8;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
+{
+	return (v & 0x7) << 13;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
+{
+	return 0x7 << 13;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
+{
+	return (v & 0xf) << 16;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
+{
+	return 0xf << 16;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
+{
+	return (v & 0xf) << 20;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
+{
+	return 0xf << 20;
+}
+static inline u32 therm_fecs_idle_filter_r(void)
+{
+	return 0x00020288;
+}
+static inline u32 therm_fecs_idle_filter_value_m(void)
+{
+	return 0xffffffff << 0;
+}
+static inline u32 therm_hubmmu_idle_filter_r(void)
+{
+	return 0x0002028c;
+}
+static inline u32 therm_hubmmu_idle_filter_value_m(void)
+{
+	return 0xffffffff << 0;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_timer_gp106.h

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_timer_gp106_h_
+#define _hw_timer_gp106_h_
+
+static inline u32 timer_pri_timeout_r(void)
+{
+	return 0x00009080;
+}
+static inline u32 timer_pri_timeout_period_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 timer_pri_timeout_period_m(void)
+{
+	return 0xffffff << 0;
+}
+static inline u32 timer_pri_timeout_period_v(u32 r)
+{
+	return (r >> 0) & 0xffffff;
+}
+static inline u32 timer_pri_timeout_en_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 timer_pri_timeout_en_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 timer_pri_timeout_en_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 timer_pri_timeout_en_en_enabled_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 timer_pri_timeout_en_en_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 timer_pri_timeout_save_0_r(void)
+{
+	return 0x00009084;
+}
+static inline u32 timer_pri_timeout_save_1_r(void)
+{
+	return 0x00009088;
+}
+static inline u32 timer_pri_timeout_fecs_errcode_r(void)
+{
+	return 0x0000908c;
+}
+static inline u32 timer_time_0_r(void)
+{
+	return 0x00009400;
+}
+static inline u32 timer_time_1_r(void)
+{
+	return 0x00009410;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_top_gp106.h

@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_top_gp106_h_
+#define _hw_top_gp106_h_
+
+static inline u32 top_num_gpcs_r(void)
+{
+	return 0x00022430;
+}
+static inline u32 top_num_gpcs_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_tpc_per_gpc_r(void)
+{
+	return 0x00022434;
+}
+static inline u32 top_tpc_per_gpc_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_num_fbps_r(void)
+{
+	return 0x00022438;
+}
+static inline u32 top_num_fbps_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_num_fbpas_r(void)
+{
+	return 0x0002243c;
+}
+static inline u32 top_num_fbpas_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_ltc_per_fbp_r(void)
+{
+	return 0x00022450;
+}
+static inline u32 top_ltc_per_fbp_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_slices_per_ltc_r(void)
+{
+	return 0x0002245c;
+}
+static inline u32 top_slices_per_ltc_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_num_ltcs_r(void)
+{
+	return 0x00022454;
+}
+static inline u32 top_device_info_r(u32 i)
+{
+	return 0x00022700 + i*4;
+}
+static inline u32 top_device_info__size_1_v(void)
+{
+	return 0x00000040;
+}
+static inline u32 top_device_info_chain_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 top_device_info_chain_enable_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 top_device_info_engine_enum_v(u32 r)
+{
+	return (r >> 26) & 0xf;
+}
+static inline u32 top_device_info_runlist_enum_v(u32 r)
+{
+	return (r >> 21) & 0xf;
+}
+static inline u32 top_device_info_intr_enum_v(u32 r)
+{
+	return (r >> 15) & 0x1f;
+}
+static inline u32 top_device_info_reset_enum_v(u32 r)
+{
+	return (r >> 9) & 0x1f;
+}
+static inline u32 top_device_info_type_enum_v(u32 r)
+{
+	return (r >> 2) & 0x1fffffff;
+}
+static inline u32 top_device_info_type_enum_graphics_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 top_device_info_type_enum_graphics_f(void)
+{
+	return 0x0;
+}
+static inline u32 top_device_info_type_enum_copy0_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 top_device_info_type_enum_copy0_f(void)
+{
+	return 0x4;
+}
+static inline u32 top_device_info_type_enum_lce_v(void)
+{
+	return 0x00000013;
+}
+static inline u32 top_device_info_type_enum_lce_f(void)
+{
+	return 0x4c;
+}
+static inline u32 top_device_info_entry_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 top_device_info_entry_not_valid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 top_device_info_entry_enum_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 top_device_info_entry_data_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 top_device_info_data_type_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 top_device_info_data_type_enum2_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 top_device_info_data_inst_id_v(u32 r)
+{
+	return (r >> 26) & 0xf;
+}
+static inline u32 top_device_info_data_pri_base_v(u32 r)
+{
+	return (r >> 12) & 0xfff;
+}
+static inline u32 top_device_info_data_pri_base_align_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
+{
+	return (r >> 3) & 0x1f;
+}
+static inline u32 top_device_info_data_fault_id_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 top_device_info_data_fault_id_valid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 top_scratch1_r(void)
+{
+	return 0x0002240c;
+}
+static inline u32 top_scratch1_devinit_completed_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_trim_gp106.h

@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_trim_gp106_h_
+#define _hw_trim_gp106_h_
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(void)
+{
+	return 0x00132924;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s(void)
+{
+	return 16;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m(void)
+{
+	return 0xffff << 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s(void)
+{
+	return 1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(u32 v)
+{
+	return (v & 0x1) << 16;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m(void)
+{
+	return 0x1 << 16;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(u32 r)
+{
+	return (r >> 16) & 0x1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f(void)
+{
+	return 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
+{
+	return 0x10000;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s(void)
+{
+	return 1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(u32 v)
+{
+	return (v & 0x1) << 20;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m(void)
+{
+	return 0x1 << 20;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(u32 r)
+{
+	return (r >> 20) & 0x1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f(void)
+{
+	return 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
+{
+	return 0x100000;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s(void)
+{
+	return 1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m(void)
+{
+	return 0x1 << 24;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(u32 r)
+{
+	return (r >> 24) & 0x1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f(void)
+{
+	return 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(void)
+{
+	return 0x70000000;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(void)
+{
+	return 0x00132928;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(void)
+{
+	return 0x00132128;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(void)
+{
+	return 0x0013212c;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_r(void)
+{
+	return 0x001373c0;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cnt_r(void)
+{
+	return 0x001373c4;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_r(void)
+{
+	return 0x001373b0;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(void)
+{
+	return 0x0;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cnt_r(void)
+{
+	return 0x001373b4;
+}
+
+#endif

drivers/gpu/nvgpu/gp106/hw_xp_gp106.h

@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xp_gp106_h_
+#define _hw_xp_gp106_h_
+
+static inline u32 xp_dl_mgr_r(u32 i)
+{
+	return 0x0008b8c0 + i*4;
+}
+static inline u32 xp_dl_mgr_safe_timing_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 xp_pl_link_config_r(u32 i)
+{
+	return 0x0008c040 + i*4;
+}
+static inline u32 xp_pl_link_config_ltssm_status_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 xp_pl_link_config_ltssm_status_idle_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_m(void)
+{
+	return 0xf << 0;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 xp_pl_link_config_max_link_rate_f(u32 v)
+{
+	return (v & 0x3) << 18;
+}
+static inline u32 xp_pl_link_config_max_link_rate_m(void)
+{
+	return 0x3 << 18;
+}
+static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 xp_pl_link_config_target_tx_width_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 xp_pl_link_config_target_tx_width_m(void)
+{
+	return 0x7 << 20;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x1_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x2_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x4_v(void)
+{
+	return 0x00000005;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x8_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x16_v(void)
+{
+	return 0x00000000;
+}
+#endif

drivers/gpu/nvgpu/gp106/hw_xve_gp106.h

@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xve_gp106_h_
+#define _hw_xve_gp106_h_
+
+static inline u32 xve_rom_ctrl_r(void)
+{
+	return 0x00000050;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
+{
+	return 0x1;
+}
+static inline u32 xve_link_control_status_r(void)
+{
+	return 0x00000088;
+}
+static inline u32 xve_link_control_status_link_speed_m(void)
+{
+	return 0xf << 16;
+}
+static inline u32 xve_link_control_status_link_speed_v(u32 r)
+{
+	return (r >> 16) & 0xf;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 xve_link_control_status_link_width_m(void)
+{
+	return 0x3f << 20;
+}
+static inline u32 xve_link_control_status_link_width_v(u32 r)
+{
+	return (r >> 20) & 0x3f;
+}
+static inline u32 xve_link_control_status_link_width_x1_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 xve_link_control_status_link_width_x2_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 xve_link_control_status_link_width_x4_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 xve_link_control_status_link_width_x8_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 xve_link_control_status_link_width_x16_v(void)
+{
+	return 0x00000010;
+}
+static inline u32 xve_priv_xv_r(void)
+{
+	return 0x00000150;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_m(void)
+{
+	return 0x1 << 7;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r)
+{
+	return (r >> 7) & 0x1;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v)
+{
+	return (v & 0x1) << 8;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_m(void)
+{
+	return 0x1 << 8;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
+{
+	return (r >> 8) & 0x1;
+}
+#endif

drivers/gpu/nvgpu/gp106/ltc_gp106.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+#include "gm20b/ltc_gm20b.h"
+#include "gp10b/ltc_gp10b.h"
+#include "gp106/ltc_gp106.h"
+
+void gp106_init_ltc(struct gpu_ops *gops)
+{
+	gp10b_init_ltc(gops);
+
+	/* dGPU does not need the LTC hack */
+	gops->ltc.cbc_fix_config = NULL;
+	gops->ltc.init_cbc = NULL;
+	gops->ltc.init_fs_state = gm20b_ltc_init_fs_state;
+}

drivers/gpu/nvgpu/gp106/ltc_gp106.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef LTC_GP106_H
+#define LTC_GP106_H
+struct gpu_ops;
+
+void gp106_init_ltc(struct gpu_ops *gops);
+#endif

drivers/gpu/nvgpu/gp106/mm_gp106.c

@@ -0,0 +1,41 @@
+/*
+ * GP106 memory management
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gp10b/mm_gp10b.h"
+#include "gp106/mm_gp106.h"
+
+#include "hw_fb_gp106.h"
+
+static size_t gp106_mm_get_vidmem_size(struct gk20a *g)
+{
+	u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r());
+	u32 mag = fb_mmu_local_memory_range_lower_mag_v(range);
+	u32 scale = fb_mmu_local_memory_range_lower_scale_v(range);
+	u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range);
+	size_t bytes = ((size_t)mag << scale) * SZ_1M;
+
+	if (ecc)
+		bytes = bytes / 16 * 15;
+
+	return bytes;
+}
+
+void gp106_init_mm(struct gpu_ops *gops)
+{
+	gp10b_init_mm(gops);
+	gops->mm.get_vidmem_size = gp106_mm_get_vidmem_size;
+	gops->mm.get_physical_addr_bits = NULL;
+}

drivers/gpu/nvgpu/gp106/mm_gp106.h

@@ -0,0 +1,23 @@
+/*
+ * GP106 memory management
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef MM_GP106_H
+#define MM_GP106_H
+
+struct gpu_ops;
+
+void gp106_init_mm(struct gpu_ops *gops);
+
+#endif

drivers/gpu/nvgpu/gp106/pmu_gp106.c

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>	/* for udelay */
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+
+#include "gm206/pmu_gm206.h"
+#include "gm20b/pmu_gm20b.h"
+#include "gp10b/pmu_gp10b.h"
+#include "gp106/pmu_gp106.h"
+#include "gp106/acr_gp106.h"
+#include "gp106/hw_psec_gp106.h"
+#include "clk/clk_mclk.h"
+#include "hw_mc_gp106.h"
+#include "hw_pwr_gp106.h"
+#include "lpwr/lpwr.h"
+#include "lpwr/rppg.h"
+
+#define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000
+#define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
+
+static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
+{
+	struct gk20a *g = gk20a_from_pmu(pmu);
+
+	gk20a_dbg_fn("");
+
+	/*
+	* From GP10X onwards, we are using PPWR_FALCON_ENGINE for reset. And as
+	* it may come into same behaviour, reading NV_PPWR_FALCON_ENGINE again
+	* after Reset.
+	*/
+
+	if (enable) {
+		int retries = PMU_MEM_SCRUBBING_TIMEOUT_MAX /
+				PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT;
+		gk20a_writel(g, pwr_falcon_engine_r(),
+			pwr_falcon_engine_reset_false_f());
+		gk20a_readl(g, pwr_falcon_engine_r());
+
+		/* make sure ELPG is in a good state */
+		if (g->ops.clock_gating.slcg_pmu_load_gating_prod)
+			g->ops.clock_gating.slcg_pmu_load_gating_prod(g,
+					g->slcg_enabled);
+		if (g->ops.clock_gating.blcg_pmu_load_gating_prod)
+			g->ops.clock_gating.blcg_pmu_load_gating_prod(g,
+					g->blcg_enabled);
+
+		/* wait for Scrubbing to complete */
+		do {
+			u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) &
+				(pwr_falcon_dmactl_dmem_scrubbing_m() |
+				 pwr_falcon_dmactl_imem_scrubbing_m());
+
+			if (!w) {
+				gk20a_dbg_fn("done");
+				return 0;
+			}
+			udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT);
+		} while (--retries || !tegra_platform_is_silicon());
+
+		/* If scrubbing timeout, keep PMU in reset state */
+		gk20a_writel(g, pwr_falcon_engine_r(),
+			pwr_falcon_engine_reset_true_f());
+		gk20a_readl(g, pwr_falcon_engine_r());
+		gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout");
+		return -ETIMEDOUT;
+	} else {
+		/* DISBALE */
+		gk20a_writel(g, pwr_falcon_engine_r(),
+			pwr_falcon_engine_reset_true_f());
+		gk20a_readl(g, pwr_falcon_engine_r());
+		return 0;
+	}
+}
+
+static int pmu_enable(struct pmu_gk20a *pmu, bool enable)
+{
+	struct gk20a *g = gk20a_from_pmu(pmu);
+	u32 reg_reset;
+	int err;
+
+	gk20a_dbg_fn("");
+
+	if (!enable) {
+		reg_reset = gk20a_readl(g, pwr_falcon_engine_r());
+		if (reg_reset !=
+			pwr_falcon_engine_reset_true_f()) {
+
+			pmu_enable_irq(pmu, false);
+			gp106_pmu_enable_hw(pmu, false);
+			udelay(10);
+		}
+	} else {
+		gp106_pmu_enable_hw(pmu, true);
+		/* TBD: post reset */
+
+		/*idle the PMU and enable interrupts on the Falcon*/
+		err = pmu_idle(pmu);
+		if (err)
+			return err;
+		udelay(5);
+		pmu_enable_irq(pmu, true);
+	}
+
+	gk20a_dbg_fn("done");
+	return 0;
+}
+
+static int gp106_pmu_reset(struct gk20a *g)
+{
+	struct pmu_gk20a *pmu = &g->pmu;
+	int err = 0;
+
+	gk20a_dbg_fn("");
+
+	err = pmu_idle(pmu);
+	if (err)
+		return err;
+
+	/* TBD: release pmu hw mutex */
+
+	err = pmu_enable(pmu, false);
+	if (err)
+		return err;
+
+	/* TBD: cancel all sequences */
+	/* TBD: init all sequences and state tables */
+	/* TBD: restore pre-init message handler */
+
+	err = pmu_enable(pmu, true);
+	if (err)
+		return err;
+
+	return err;
+}
+
+static int gp106_sec2_reset(struct gk20a *g)
+{
+	gk20a_dbg_fn("");
+	//sec2 reset
+	gk20a_writel(g, psec_falcon_engine_r(),
+			pwr_falcon_engine_reset_true_f());
+	udelay(10);
+	gk20a_writel(g, psec_falcon_engine_r(),
+			pwr_falcon_engine_reset_false_f());
+
+	gk20a_dbg_fn("done");
+	return 0;
+}
+
+static int gp106_falcon_reset(struct gk20a *g)
+{
+	gk20a_dbg_fn("");
+
+	gp106_pmu_reset(g);
+	gp106_sec2_reset(g);
+
+	gk20a_dbg_fn("done");
+	return 0;
+}
+
+static bool gp106_is_pmu_supported(struct gk20a *g)
+{
+	return true;
+}
+
+static u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id)
+{
+	if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS)
+		return PMU_PG_FEATURE_GR_RPPG_ENABLED;
+
+	if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS)
+		return NVGPU_PMU_MS_FEATURE_MASK_ALL;
+
+	return 0;
+}
+
+static u32 gp106_pmu_pg_engines_list(struct gk20a *g)
+{
+	return BIT(PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
+			BIT(PMU_PG_ELPG_ENGINE_ID_MS);
+}
+
+static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg,
+			void *param, u32 handle, u32 status)
+{
+	gk20a_dbg_fn("");
+
+	if (status != 0) {
+		gk20a_err(dev_from_gk20a(g), "PG PARAM cmd aborted");
+		return;
+	}
+
+	gp106_dbg_pmu("PG PARAM is acknowledged from PMU %x",
+			msg->msg.pg.msg_type);
+}
+
+static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
+{
+	struct pmu_gk20a *pmu = &g->pmu;
+	struct pmu_cmd cmd;
+	u32 seq;
+	u32 status;
+
+	memset(&cmd, 0, sizeof(struct pmu_cmd));
+	if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) {
+
+		status = init_rppg(g);
+		if (status != 0) {
+			gk20a_err(dev_from_gk20a(g), "RPPG init Failed");
+			return -1;
+		}
+
+		cmd.hdr.unit_id = PMU_UNIT_PG;
+		cmd.hdr.size = PMU_CMD_HDR_SIZE +
+				sizeof(struct pmu_pg_cmd_gr_init_param);
+		cmd.cmd.pg.gr_init_param.cmd_type =
+				PMU_PG_CMD_ID_PG_PARAM;
+		cmd.cmd.pg.gr_init_param.sub_cmd_id =
+				PMU_PG_PARAM_CMD_GR_INIT_PARAM;
+		cmd.cmd.pg.gr_init_param.featuremask =
+				PMU_PG_FEATURE_GR_RPPG_ENABLED;
+
+		gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM");
+		gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+				pmu_handle_param_msg, pmu, &seq, ~0);
+	} else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) {
+		cmd.hdr.unit_id = PMU_UNIT_PG;
+		cmd.hdr.size = PMU_CMD_HDR_SIZE +
+			sizeof(struct pmu_pg_cmd_ms_init_param);
+		cmd.cmd.pg.ms_init_param.cmd_type =
+			PMU_PG_CMD_ID_PG_PARAM;
+		cmd.cmd.pg.ms_init_param.cmd_id =
+			PMU_PG_PARAM_CMD_MS_INIT_PARAM;
+		cmd.cmd.pg.ms_init_param.support_mask =
+			NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |
+			NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |
+			NVGPU_PMU_MS_FEATURE_MASK_RPPG |
+			NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING;
+
+		gp106_dbg_pmu("cmd post MS PMU_PG_CMD_ID_PG_PARAM");
+		gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+			pmu_handle_param_msg, pmu, &seq, ~0);
+	}
+
+	return 0;
+}
+
+void gp106_init_pmu_ops(struct gpu_ops *gops)
+{
+	gk20a_dbg_fn("");
+
+	if (gops->privsecurity) {
+		gp106_init_secure_pmu(gops);
+		gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
+		gops->pmu.load_lsfalcon_ucode = gm206_load_falcon_ucode;
+		gops->pmu.is_lazy_bootstrap = gm206_is_lazy_bootstrap;
+		gops->pmu.is_priv_load = gm206_is_priv_load;
+	} else {
+		gk20a_init_pmu_ops(gops);
+		gops->pmu.pmu_setup_hw_and_bootstrap =
+			gm20b_init_nspmu_setup_hw1;
+		gops->pmu.load_lsfalcon_ucode = NULL;
+		gops->pmu.init_wpr_region = NULL;
+	}
+	gops->pmu.pmu_setup_elpg = NULL;
+	gops->pmu.lspmuwprinitdone = 0;
+	gops->pmu.fecsbootstrapdone = false;
+	gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase;
+	gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics;
+	gops->pmu.pmu_pg_init_param = gp106_pg_param_init;
+	gops->pmu.pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list;
+	gops->pmu.pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list;
+	gops->pmu.pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg;
+	gops->pmu.pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg;
+	gops->pmu.pmu_pg_param_post_init = nvgpu_lpwr_post_init;
+	gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
+	gops->pmu.dump_secure_fuses = NULL;
+	gops->pmu.reset = gp106_falcon_reset;
+	gops->pmu.mclk_init = clk_mclkseq_init_mclk_gddr5;
+	gops->pmu.is_pmu_supported = gp106_is_pmu_supported;
+
+	gk20a_dbg_fn("done");
+}

drivers/gpu/nvgpu/gp106/pmu_gp106.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __PMU_GP106_H_
+#define __PMU_GP106_H_
+
+#define gp106_dbg_pmu(fmt, arg...) \
+	gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
+
+void gp106_init_pmu_ops(struct gpu_ops *gops);
+
+#endif /*__PMU_GP106_H_*/

drivers/gpu/nvgpu/gp106/regops_gp106.h

@@ -0,0 +1,24 @@
+/*
+ *
+ * Tegra GP106 GPU Debugger Driver Register Ops
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __REGOPS_GP106_H_
+#define __REGOPS_GP106_H_
+
+void gp106_init_regops(struct gpu_ops *gops);
+
+#endif /* __REGOPS_GP106_H_ */

drivers/gpu/nvgpu/gp106/sec2_gp106.c

@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>	/* for udelay */
+#include <linux/clk.h>
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+
+#include "gm206/pmu_gm206.h"
+#include "gm20b/pmu_gm20b.h"
+#include "gp10b/pmu_gp10b.h"
+#include "gp106/pmu_gp106.h"
+#include "gp106/acr_gp106.h"
+#include "gp106/hw_mc_gp106.h"
+#include "gp106/hw_pwr_gp106.h"
+#include "gp106/hw_psec_gp106.h"
+#include "sec2_gp106.h"
+#include "acr.h"
+
+/*Defines*/
+#define gm20b_dbg_pmu(fmt, arg...) \
+	gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
+
+int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout)
+{
+	u32 data = 0;
+	unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+
+	while (time_before(jiffies, end_jiffies) ||
+			!tegra_platform_is_silicon()) {
+		gk20a_writel(g, psec_falcon_irqsclr_r(),
+			     gk20a_readl(g, psec_falcon_irqsclr_r()) | (0x10));
+		data = gk20a_readl(g, psec_falcon_irqstat_r());
+		if ((data & psec_falcon_irqstat_halt_true_f()) !=
+			psec_falcon_irqstat_halt_true_f())
+			/*halt irq is clear*/
+			break;
+		timeout--;
+		udelay(1);
+	}
+	if (timeout == 0)
+		return -EBUSY;
+	return 0;
+}
+
+int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
+{
+	u32 data = 0;
+	int completion = -EBUSY;
+	unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+
+	while (time_before(jiffies, end_jiffies) ||
+			!tegra_platform_is_silicon()) {
+		data = gk20a_readl(g, psec_falcon_cpuctl_r());
+		if (data & psec_falcon_cpuctl_halt_intr_m()) {
+			/*CPU is halted break*/
+			completion = 0;
+			break;
+		}
+		udelay(1);
+	}
+	if (completion){
+		gk20a_err(dev_from_gk20a(g), "ACR boot timed out");
+	}
+	else {
+
+		g->acr.capabilities = gk20a_readl(g, psec_falcon_mailbox1_r());
+		gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities);
+		data = gk20a_readl(g, psec_falcon_mailbox0_r());
+		if (data) {
+
+			gk20a_err(dev_from_gk20a(g),
+				"ACR boot failed, err %x", data);
+			completion = -EAGAIN;
+		}
+	}
+
+	init_pmu_setup_hw1(g);
+
+	return completion;
+}
+
+void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
+		u32 dst, u8 *src, u32 size, u8 port)
+{
+	struct gk20a *g = gk20a_from_pmu(pmu);
+	u32 i, words, bytes;
+	u32 data, addr_mask;
+	u32 *src_u32 = (u32*)src;
+
+	if (size == 0) {
+		gk20a_err(dev_from_gk20a(g),
+			"size is zero");
+		return;
+	}
+
+	if (dst & 0x3) {
+		gk20a_err(dev_from_gk20a(g),
+			"dst (0x%08x) not 4-byte aligned", dst);
+		return;
+	}
+
+	mutex_lock(&pmu->pmu_copy_lock);
+
+	words = size >> 2;
+	bytes = size & 0x3;
+
+	addr_mask = psec_falcon_dmemc_offs_m() |
+		    psec_falcon_dmemc_blk_m();
+
+	dst &= addr_mask;
+
+	gk20a_writel(g, psec_falcon_dmemc_r(port),
+		dst | psec_falcon_dmemc_aincw_f(1));
+
+	for (i = 0; i < words; i++)
+		gk20a_writel(g, psec_falcon_dmemd_r(port), src_u32[i]);
+
+	if (bytes > 0) {
+		data = 0;
+		for (i = 0; i < bytes; i++)
+			((u8 *)&data)[i] = src[(words << 2) + i];
+		gk20a_writel(g, psec_falcon_dmemd_r(port), data);
+	}
+
+	data = gk20a_readl(g, psec_falcon_dmemc_r(port)) & addr_mask;
+	size = ALIGN(size, 4);
+	if (data != dst + size) {
+		gk20a_err(dev_from_gk20a(g),
+			"copy failed. bytes written %d, expected %d",
+			data - dst, size);
+	}
+	mutex_unlock(&pmu->pmu_copy_lock);
+	return;
+}
+
+int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
+	void *desc, u32 bl_sz)
+{
+	struct gk20a *g = gk20a_from_pmu(pmu);
+	struct acr_desc *acr = &g->acr;
+	struct mm_gk20a *mm = &g->mm;
+	u32 imem_dst_blk = 0;
+	u32 virt_addr = 0;
+	u32 tag = 0;
+	u32 index = 0;
+	struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc;
+	u32 *bl_ucode;
+	u32 data = 0;
+
+	gk20a_dbg_fn("");
+
+	/* SEC2 Config */
+	gk20a_writel(g, psec_falcon_itfen_r(),
+			gk20a_readl(g, psec_falcon_itfen_r()) |
+			psec_falcon_itfen_ctxen_enable_f());
+
+	gk20a_writel(g, psec_falcon_nxtctx_r(),
+			pwr_pmu_new_instblk_ptr_f(
+			gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
+			pwr_pmu_new_instblk_valid_f(1) |
+			gk20a_aperture_mask(g, &mm->pmu.inst_block,
+				pwr_pmu_new_instblk_target_sys_coh_f(),
+				pwr_pmu_new_instblk_target_fb_f()));
+
+	data = gk20a_readl(g, psec_falcon_debug1_r());
+	data |= psec_falcon_debug1_ctxsw_mode_m();
+	gk20a_writel(g, psec_falcon_debug1_r(), data);
+
+	data = gk20a_readl(g, psec_falcon_engctl_r());
+	data |= (1 << 3);
+	gk20a_writel(g, psec_falcon_engctl_r(), data);
+
+	/* TBD: load all other surfaces */
+	/*copy bootloader interface structure to dmem*/
+	gk20a_writel(g, psec_falcon_dmemc_r(0),
+			psec_falcon_dmemc_offs_f(0) |
+			psec_falcon_dmemc_blk_f(0)  |
+			psec_falcon_dmemc_aincw_f(1));
+	sec2_copy_to_dmem(pmu, 0, (u8 *)desc,
+		sizeof(struct flcn_bl_dmem_desc), 0);
+	/*TODO This had to be copied to bl_desc_dmem_load_off, but since
+	 * this is 0, so ok for now*/
+
+	/* Now copy bootloader to TOP of IMEM */
+	imem_dst_blk = (psec_falcon_hwcfg_imem_size_v(
+			gk20a_readl(g, psec_falcon_hwcfg_r()))) - bl_sz/256;
+
+	/* Set Auto-Increment on write */
+	gk20a_writel(g, psec_falcon_imemc_r(0),
+			psec_falcon_imemc_offs_f(0) |
+			psec_falcon_imemc_blk_f(imem_dst_blk)  |
+			psec_falcon_imemc_aincw_f(1));
+	virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
+	tag = virt_addr >> 8; /* tag is always 256B aligned */
+	bl_ucode = (u32 *)(acr->hsbl_ucode.cpu_va);
+	for (index = 0; index < bl_sz/4; index++) {
+		if ((index % 64) == 0) {
+			gk20a_writel(g, psec_falcon_imemt_r(0),
+				(tag & 0xffff) << 0);
+			tag++;
+		}
+		gk20a_writel(g, psec_falcon_imemd_r(0),
+				bl_ucode[index] & 0xffffffff);
+	}
+	gk20a_writel(g, psec_falcon_imemt_r(0), (0 & 0xffff) << 0);
+
+	gm20b_dbg_pmu("Before starting falcon with BL\n");
+
+	gk20a_writel(g, psec_falcon_mailbox0_r(), 0xDEADA5A5);
+
+	gk20a_writel(g, psec_falcon_bootvec_r(),
+			psec_falcon_bootvec_vec_f(virt_addr));
+
+	gk20a_writel(g, psec_falcon_cpuctl_r(),
+			psec_falcon_cpuctl_startcpu_f(1));
+
+	return 0;
+}
+
+void sec_enable_irq(struct pmu_gk20a *pmu, bool enable)
+{
+	struct gk20a *g = gk20a_from_pmu(pmu);
+
+	gk20a_dbg_fn("");
+
+	gk20a_writel(g, psec_falcon_irqmclr_r(),
+		psec_falcon_irqmclr_gptmr_f(1)  |
+		psec_falcon_irqmclr_wdtmr_f(1)  |
+		psec_falcon_irqmclr_mthd_f(1)   |
+		psec_falcon_irqmclr_ctxsw_f(1)  |
+		psec_falcon_irqmclr_halt_f(1)   |
+		psec_falcon_irqmclr_exterr_f(1) |
+		psec_falcon_irqmclr_swgen0_f(1) |
+		psec_falcon_irqmclr_swgen1_f(1) |
+		psec_falcon_irqmclr_ext_f(0xff));
+
+	if (enable) {
+		/* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */
+		gk20a_writel(g, psec_falcon_irqdest_r(),
+			psec_falcon_irqdest_host_gptmr_f(0)    |
+			psec_falcon_irqdest_host_wdtmr_f(1)    |
+			psec_falcon_irqdest_host_mthd_f(0)     |
+			psec_falcon_irqdest_host_ctxsw_f(0)    |
+			psec_falcon_irqdest_host_halt_f(1)     |
+			psec_falcon_irqdest_host_exterr_f(0)   |
+			psec_falcon_irqdest_host_swgen0_f(1)   |
+			psec_falcon_irqdest_host_swgen1_f(0)   |
+			psec_falcon_irqdest_host_ext_f(0xff)   |
+			psec_falcon_irqdest_target_gptmr_f(1)  |
+			psec_falcon_irqdest_target_wdtmr_f(0)  |
+			psec_falcon_irqdest_target_mthd_f(0)   |
+			psec_falcon_irqdest_target_ctxsw_f(0)  |
+			psec_falcon_irqdest_target_halt_f(0)   |
+			psec_falcon_irqdest_target_exterr_f(0) |
+			psec_falcon_irqdest_target_swgen0_f(0) |
+			psec_falcon_irqdest_target_swgen1_f(1) |
+			psec_falcon_irqdest_target_ext_f(0xff));
+
+		/* 0=disable, 1=enable */
+		gk20a_writel(g, psec_falcon_irqmset_r(),
+			psec_falcon_irqmset_gptmr_f(1)  |
+			psec_falcon_irqmset_wdtmr_f(1)  |
+			psec_falcon_irqmset_mthd_f(0)   |
+			psec_falcon_irqmset_ctxsw_f(0)  |
+			psec_falcon_irqmset_halt_f(1)   |
+			psec_falcon_irqmset_exterr_f(1) |
+			psec_falcon_irqmset_swgen0_f(1) |
+			psec_falcon_irqmset_swgen1_f(1));
+
+	}
+
+	gk20a_dbg_fn("done");
+}
+
+void init_pmu_setup_hw1(struct gk20a *g)
+{
+	struct mm_gk20a *mm = &g->mm;
+	struct pmu_gk20a *pmu = &g->pmu;
+	struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+
+	/* PMU TRANSCFG */
+	/* setup apertures - virtual */
+	gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+			pwr_fbif_transcfg_mem_type_physical_f() |
+			pwr_fbif_transcfg_target_local_fb_f());
+	gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+			pwr_fbif_transcfg_mem_type_virtual_f());
+	/* setup apertures - physical */
+	gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+			pwr_fbif_transcfg_mem_type_physical_f() |
+			pwr_fbif_transcfg_target_local_fb_f());
+	gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+			pwr_fbif_transcfg_mem_type_physical_f() |
+			pwr_fbif_transcfg_target_coherent_sysmem_f());
+	gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+			pwr_fbif_transcfg_mem_type_physical_f() |
+			pwr_fbif_transcfg_target_noncoherent_sysmem_f());
+
+	/* PMU Config */
+	gk20a_writel(g, pwr_falcon_itfen_r(),
+				gk20a_readl(g, pwr_falcon_itfen_r()) |
+				pwr_falcon_itfen_ctxen_enable_f());
+	gk20a_writel(g, pwr_pmu_new_instblk_r(),
+				pwr_pmu_new_instblk_ptr_f(
+					gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
+				pwr_pmu_new_instblk_valid_f(1) |
+				gk20a_aperture_mask(g, &mm->pmu.inst_block,
+					pwr_pmu_new_instblk_target_sys_coh_f(),
+					pwr_pmu_new_instblk_target_fb_f()));
+
+	/*Copying pmu cmdline args*/
+	g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
+				clk_get_rate(platform->clk[1]));
+	g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
+	g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
+		pmu, GK20A_PMU_TRACE_BUFSIZE);
+	g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
+	g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
+		pmu, GK20A_PMU_DMAIDX_VIRT);
+
+	pmu_copy_to_dmem(pmu, g->acr.pmu_args,
+			(u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
+			g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
+
+}
+
+int init_sec2_setup_hw1(struct gk20a *g,
+		void *desc, u32 bl_sz)
+{
+	struct pmu_gk20a *pmu = &g->pmu;
+	int err;
+	u32 data = 0;
+
+	gk20a_dbg_fn("");
+
+	mutex_lock(&pmu->isr_mutex);
+	g->ops.pmu.reset(g);
+	pmu->isr_enabled = true;
+	mutex_unlock(&pmu->isr_mutex);
+
+	data = gk20a_readl(g, psec_fbif_ctl_r());
+	data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f();
+	gk20a_writel(g, psec_fbif_ctl_r(), data);
+
+	data = gk20a_readl(g, psec_falcon_dmactl_r());
+	data &= ~(psec_falcon_dmactl_require_ctx_f(1));
+	gk20a_writel(g, psec_falcon_dmactl_r(), data);
+
+	/* setup apertures - virtual */
+	gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+			psec_fbif_transcfg_mem_type_physical_f() |
+			psec_fbif_transcfg_target_local_fb_f());
+	gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+			psec_fbif_transcfg_mem_type_virtual_f());
+	/* setup apertures - physical */
+	gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+			psec_fbif_transcfg_mem_type_physical_f() |
+			psec_fbif_transcfg_target_local_fb_f());
+	gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+			psec_fbif_transcfg_mem_type_physical_f() |
+			psec_fbif_transcfg_target_coherent_sysmem_f());
+	gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+			psec_fbif_transcfg_mem_type_physical_f() |
+			psec_fbif_transcfg_target_noncoherent_sysmem_f());
+
+	/*disable irqs for hs falcon booting as we will poll for halt*/
+	mutex_lock(&pmu->isr_mutex);
+	pmu_enable_irq(pmu, false);
+	sec_enable_irq(pmu, false);
+	pmu->isr_enabled = false;
+	mutex_unlock(&pmu->isr_mutex);
+	err = bl_bootstrap_sec2(pmu, desc, bl_sz);
+	if (err)
+		return err;
+
+	return 0;
+}

drivers/gpu/nvgpu/gp106/sec2_gp106.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __SEC2_H_
+#define __SEC2_H_
+
+int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
+int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
+void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
+		u32 dst, u8 *src, u32 size, u8 port);
+void sec2_dump_falcon_stats(struct pmu_gk20a *pmu);
+int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
+	void *desc, u32 bl_sz);
+void sec_enable_irq(struct pmu_gk20a *pmu, bool enable);
+void init_pmu_setup_hw1(struct gk20a *g);
+int init_sec2_setup_hw1(struct gk20a *g,
+		void *desc, u32 bl_sz);
+
+#endif /*__SEC2_H_*/

drivers/gpu/nvgpu/gp106/therm_gp106.c

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "therm_gp106.h"
+#include <linux/debugfs.h>
+#include "hw_therm_gp106.h"
+
+static void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8)
+{
+	*max_24_8 = (0x87 << 8);
+	*min_24_8 = ((-216) << 8);
+}
+
+static int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8)
+{
+	int err = 0;
+	u32 readval;
+
+	readval = gk20a_readl(g, therm_temp_sensor_tsense_r());
+
+	if (!(therm_temp_sensor_tsense_state_v(readval) &
+		therm_temp_sensor_tsense_state_valid_v())) {
+		gk20a_err(dev_from_gk20a(g),
+			"Attempt to read temperature while sensor is OFF!\n");
+		err = -EINVAL;
+	} else if (therm_temp_sensor_tsense_state_v(readval) &
+		therm_temp_sensor_tsense_state_shadow_v()) {
+		gk20a_err(dev_from_gk20a(g),
+			"Reading temperature from SHADOWed sensor!\n");
+	}
+
+	// Convert from F9.5 -> F27.5 -> F24.8.
+	readval &= therm_temp_sensor_tsense_fixed_point_m();
+
+	*temp_f24_8 = readval;
+
+	return err;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int therm_get_internal_sensor_curr_temp(void *data, u64 *val)
+{
+	struct gk20a *g = (struct gk20a *)data;
+	u32 readval;
+	int err;
+
+	err = gp106_get_internal_sensor_curr_temp(g, &readval);
+	if (!err)
+		*val = readval;
+
+	return err;
+}
+DEFINE_SIMPLE_ATTRIBUTE(therm_ctrl_fops, therm_get_internal_sensor_curr_temp, NULL, "%llu\n");
+
+static void gp106_therm_debugfs_init(struct gk20a *g) {
+	struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+	struct dentry *dbgentry;
+
+	dbgentry = debugfs_create_file(
+		"temp", S_IRUGO, platform->debugfs, g, &therm_ctrl_fops);
+	if (!dbgentry)
+		gk20a_err(dev_from_gk20a(g), "debugfs entry create failed for therm_curr_temp");
+}
+#endif
+
+static int gp106_elcg_init_idle_filters(struct gk20a *g)
+{
+	u32 gate_ctrl, idle_filter;
+	u32 engine_id;
+	u32 active_engine_id = 0;
+	struct fifo_gk20a *f = &g->fifo;
+
+	gk20a_dbg_fn("");
+
+	for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
+		active_engine_id = f->active_engines_list[engine_id];
+		gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
+
+		if (tegra_platform_is_linsim()) {
+			gate_ctrl = set_field(gate_ctrl,
+				therm_gate_ctrl_eng_delay_after_m(),
+				therm_gate_ctrl_eng_delay_after_f(4));
+		}
+
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_idle_filt_exp_m(),
+			therm_gate_ctrl_eng_idle_filt_exp_f(2));
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_idle_filt_mant_m(),
+			therm_gate_ctrl_eng_idle_filt_mant_f(1));
+		gate_ctrl = set_field(gate_ctrl,
+			therm_gate_ctrl_eng_delay_before_m(),
+			therm_gate_ctrl_eng_delay_before_f(0));
+		gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
+	}
+
+	/* default fecs_idle_filter to 0 */
+	idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
+	idle_filter &= ~therm_fecs_idle_filter_value_m();
+	gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
+	/* default hubmmu_idle_filter to 0 */
+	idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
+	idle_filter &= ~therm_hubmmu_idle_filter_value_m();
+	gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
+
+	gk20a_dbg_fn("done");
+	return 0;
+}
+
+void gp106_init_therm_ops(struct gpu_ops *gops) {
+#ifdef CONFIG_DEBUG_FS
+	gops->therm.therm_debugfs_init = gp106_therm_debugfs_init;
+#endif
+	gops->therm.elcg_init_idle_filters = gp106_elcg_init_idle_filters;
+	gops->therm.get_internal_sensor_curr_temp = gp106_get_internal_sensor_curr_temp;
+	gops->therm.get_internal_sensor_limits =
+			gp106_get_internal_sensor_limits;
+}

drivers/gpu/nvgpu/gp106/therm_gp106.h

@@ -0,0 +1,22 @@
+/*
+ * general thermal control structures & definitions
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef NVGPU_THERM_GP106_H
+#define NVGPU_THERM_GP106_H
+
+#include "gk20a/gk20a.h"
+
+void gp106_init_therm_ops(struct gpu_ops *gops);
+#endif

drivers/gpu/nvgpu/gp106/xve_gp106.c

@@ -0,0 +1,623 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/debugfs.h>
+
+#include "gk20a/gk20a.h"
+#include "gm206/bios_gm206.h"
+#include "gp106/xve_gp106.h"
+
+#include "gp106/hw_xp_gp106.h"
+#include "gp106/hw_xve_gp106.h"
+
+/**
+ * Init a timer and place the timeout data in @timeout.
+ */
+static void init_timeout(u32 timeout_ms, u32 *timeout)
+{
+	*timeout = jiffies + msecs_to_jiffies(timeout_ms);
+}
+
+/**
+ * Returns 1 if the current time is after @timeout i.e: the timer timed
+ * out. Returns 0 if the timer still has time left.
+ */
+static int check_timeout(u32 *timeout)
+{
+	unsigned long now = jiffies;
+	unsigned long timeout_l = (unsigned long)*timeout;
+
+	if (time_after(now, timeout_l))
+		return 1;
+
+	return 0;
+}
+
+static void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val)
+{
+	gk20a_writel(g, NV_PCFG + reg, val);
+}
+
+static u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg)
+{
+	return gk20a_readl(g, NV_PCFG + reg);
+}
+
+/**
+ * Places one of:
+ *
+ *   %GPU_XVE_SPEED_2P5
+ *   %GPU_XVE_SPEED_5P0
+ *   %GPU_XVE_SPEED_8P0
+ *
+ * in the u32 pointed to by @xve_link_speed. If for some reason an unknown PCIe
+ * bus speed is detected then *@xve_link_speed is not touched and -ENODEV is
+ * returned.
+ */
+static int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed)
+{
+	u32 status;
+	u32 link_speed, real_link_speed = 0;
+
+	status = g->ops.xve.xve_readl(g, xve_link_control_status_r());
+
+	link_speed = xve_link_control_status_link_speed_v(status);
+
+	/*
+	 * Can't use a switch statement becuase switch statements dont work with
+	 * function calls.
+	 */
+	if (link_speed == xve_link_control_status_link_speed_link_speed_2p5_v())
+		real_link_speed = GPU_XVE_SPEED_2P5;
+	if (link_speed == xve_link_control_status_link_speed_link_speed_5p0_v())
+		real_link_speed = GPU_XVE_SPEED_5P0;
+	if (link_speed == xve_link_control_status_link_speed_link_speed_8p0_v())
+		real_link_speed = GPU_XVE_SPEED_8P0;
+
+	if (!real_link_speed) {
+		pr_warn("%s: Unknown PCIe bus speed!\n", __func__);
+		return -ENODEV;
+	}
+
+	*xve_link_speed = real_link_speed;
+	return 0;
+}
+
+/**
+ * Set the mask for L0s in the XVE.
+ *
+ * When @status is non-zero the mask for L0s is set which _disables_ L0s. When
+ * @status is zero L0s is no longer masked and may be enabled.
+ */
+static void set_xve_l0s_mask(struct gk20a *g, bool status)
+{
+	u32 xve_priv;
+	u32 status_bit = status ? 1 : 0;
+
+	xve_priv = g->ops.xve.xve_readl(g, xve_priv_xv_r());
+
+	xve_priv = set_field(xve_priv,
+		  xve_priv_xv_cya_l0s_enable_m(),
+		  xve_priv_xv_cya_l0s_enable_f(status_bit));
+
+	g->ops.xve.xve_writel(g, xve_priv_xv_r(), xve_priv);
+}
+
+/**
+ * Set the mask for L1 in the XVE.
+ *
+ * When @status is non-zero the mask for L1 is set which _disables_ L0s. When
+ * @status is zero L1 is no longer masked and may be enabled.
+ */
+static void set_xve_l1_mask(struct gk20a *g, int status)
+{
+	u32 xve_priv;
+	u32 status_bit = status ? 1 : 0;
+
+	xve_priv = g->ops.xve.xve_readl(g, xve_priv_xv_r());
+
+	xve_priv = set_field(xve_priv,
+		  xve_priv_xv_cya_l1_enable_m(),
+		  xve_priv_xv_cya_l1_enable_f(status_bit));
+
+	g->ops.xve.xve_writel(g, xve_priv_xv_r(), xve_priv);
+}
+
+/**
+ * When doing the speed change disable power saving features.
+ */
+static void disable_aspm_gp106(struct gk20a *g)
+{
+	u32 xve_priv;
+
+	xve_priv = g->ops.xve.xve_readl(g, xve_priv_xv_r());
+
+	/*
+	 * Store prior ASPM state so we can restore it later on.
+	 */
+	g->xve_l0s = xve_priv_xv_cya_l0s_enable_v(xve_priv);
+	g->xve_l1  = xve_priv_xv_cya_l1_enable_v(xve_priv);
+
+	set_xve_l0s_mask(g, true);
+	set_xve_l1_mask(g, true);
+}
+
+/**
+ * Restore the state saved by disable_aspm_gp106().
+ */
+static void enable_aspm_gp106(struct gk20a *g)
+{
+	set_xve_l0s_mask(g, g->xve_l0s);
+	set_xve_l1_mask(g, g->xve_l1);
+}
+
+/*
+ * Error checking is done in xve_set_speed_gp106.
+ */
+static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
+{
+	u32 current_link_speed, new_link_speed;
+	u32 dl_mgr, saved_dl_mgr;
+	u32 pl_link_config;
+	u32 link_control_status, link_speed_setting, link_width;
+	u32 timeout;
+	int attempts = 10, err_status = 0;
+
+	g->ops.xve.get_speed(g, &current_link_speed);
+	xv_sc_dbg(PRE_CHANGE, "Executing PCIe link change.");
+	xv_sc_dbg(PRE_CHANGE, "  Current speed:  %s",
+		  xve_speed_to_str(current_link_speed));
+	xv_sc_dbg(PRE_CHANGE, "  Next speed:     %s",
+		  xve_speed_to_str(next_link_speed));
+	xv_sc_dbg(PRE_CHANGE, "  PL_LINK_CONFIG: 0x%08x",
+		  gk20a_readl(g, xp_pl_link_config_r(0)));
+
+	xv_sc_dbg(DISABLE_ASPM, "Disabling ASPM...");
+	disable_aspm_gp106(g);
+	xv_sc_dbg(DISABLE_ASPM, "  Done!");
+
+	xv_sc_dbg(DL_SAFE_MODE, "Putting DL in safe mode...");
+	saved_dl_mgr = gk20a_readl(g, xp_dl_mgr_r(0));
+
+	/*
+	 * Put the DL in safe mode.
+	 */
+	dl_mgr = saved_dl_mgr;
+	dl_mgr |= xp_dl_mgr_safe_timing_f(1);
+	gk20a_writel(g, xp_dl_mgr_r(0), dl_mgr);
+	xv_sc_dbg(DL_SAFE_MODE, "  Done!");
+
+	init_timeout(GPU_XVE_TIMEOUT_MS, &timeout);
+
+	xv_sc_dbg(CHECK_LINK, "Checking for link idle...");
+	while (1) {
+		pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0));
+		if ((xp_pl_link_config_ltssm_status_f(pl_link_config) ==
+		     xp_pl_link_config_ltssm_status_idle_v()) &&
+		    (xp_pl_link_config_ltssm_directive_f(pl_link_config) ==
+		     xp_pl_link_config_ltssm_directive_normal_operations_v()))
+			break;
+
+		if (check_timeout(&timeout)) {
+			err_status = -ETIMEDOUT;
+			break;
+		}
+	}
+
+	if (err_status == -ETIMEDOUT)
+		/* TODO: debug message. */
+		goto done;
+
+	xv_sc_dbg(CHECK_LINK, "  Done");
+
+	xv_sc_dbg(LINK_SETTINGS, "Preparing next link settings");
+	pl_link_config &= ~xp_pl_link_config_max_link_rate_m();
+	switch (next_link_speed) {
+	case GPU_XVE_SPEED_2P5:
+		link_speed_setting =
+			xve_link_control_status_link_speed_link_speed_2p5_v();
+		pl_link_config |= xp_pl_link_config_max_link_rate_f(
+			xp_pl_link_config_max_link_rate_2500_mtps_v());
+		break;
+	case GPU_XVE_SPEED_5P0:
+		link_speed_setting =
+			xve_link_control_status_link_speed_link_speed_5p0_v();
+		pl_link_config |= xp_pl_link_config_max_link_rate_f(
+			xp_pl_link_config_max_link_rate_5000_mtps_v());
+		break;
+	case GPU_XVE_SPEED_8P0:
+		link_speed_setting =
+			xve_link_control_status_link_speed_link_speed_8p0_v();
+		pl_link_config |= xp_pl_link_config_max_link_rate_f(
+			xp_pl_link_config_max_link_rate_8000_mtps_v());
+		break;
+	default:
+		BUG(); /* Should never be hit. */
+	}
+
+	link_control_status =
+		g->ops.xve.xve_readl(g, xve_link_control_status_r());
+	link_width = xve_link_control_status_link_width_v(link_control_status);
+
+	pl_link_config &= ~xp_pl_link_config_target_tx_width_m();
+
+	/* Can't use a switch due to oddities in register definitions. */
+	if (link_width == xve_link_control_status_link_width_x1_v())
+		pl_link_config |= xp_pl_link_config_target_tx_width_f(
+			xp_pl_link_config_target_tx_width_x1_v());
+	else if (link_width == xve_link_control_status_link_width_x2_v())
+		pl_link_config |= xp_pl_link_config_target_tx_width_f(
+			xp_pl_link_config_target_tx_width_x2_v());
+	else if (link_width == xve_link_control_status_link_width_x4_v())
+		pl_link_config |= xp_pl_link_config_target_tx_width_f(
+			xp_pl_link_config_target_tx_width_x4_v());
+	else if (link_width == xve_link_control_status_link_width_x8_v())
+		pl_link_config |= xp_pl_link_config_target_tx_width_f(
+			xp_pl_link_config_target_tx_width_x8_v());
+	else if (link_width == xve_link_control_status_link_width_x16_v())
+		pl_link_config |= xp_pl_link_config_target_tx_width_f(
+			xp_pl_link_config_target_tx_width_x16_v());
+	else
+		BUG();
+
+	xv_sc_dbg(LINK_SETTINGS, "  pl_link_config = 0x%08x", pl_link_config);
+	xv_sc_dbg(LINK_SETTINGS, "  Done");
+
+	xv_sc_dbg(EXEC_CHANGE, "Running link speed change...");
+
+	init_timeout(GPU_XVE_TIMEOUT_MS, &timeout);
+	while (1) {
+		gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config);
+		if (pl_link_config ==
+		    gk20a_readl(g, xp_pl_link_config_r(0)))
+			break;
+
+		if (check_timeout(&timeout)) {
+			err_status = -ETIMEDOUT;
+			break;
+		}
+	}
+
+	if (err_status == -ETIMEDOUT)
+		goto done;
+
+	xv_sc_dbg(EXEC_CHANGE, "  Wrote PL_LINK_CONFIG.");
+
+	pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0));
+
+	do {
+		pl_link_config = set_field(pl_link_config,
+			  xp_pl_link_config_ltssm_directive_m(),
+			  xp_pl_link_config_ltssm_directive_f(
+			  xp_pl_link_config_ltssm_directive_change_speed_v()));
+
+		xv_sc_dbg(EXEC_CHANGE, "  Executing change (0x%08x)!",
+			  pl_link_config);
+		gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config);
+
+		/*
+		 * Read NV_XP_PL_LINK_CONFIG until the link has swapped to
+		 * the target speed.
+		 */
+		init_timeout(GPU_XVE_TIMEOUT_MS, &timeout);
+		while (1) {
+			pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0));
+			if (pl_link_config != 0xfffffff &&
+			    (xp_pl_link_config_ltssm_status_f(pl_link_config) ==
+			     xp_pl_link_config_ltssm_status_idle_v()) &&
+			    (xp_pl_link_config_ltssm_directive_f(pl_link_config) ==
+			     xp_pl_link_config_ltssm_directive_normal_operations_v()))
+				break;
+
+			if (check_timeout(&timeout)) {
+				err_status = -ETIMEDOUT;
+				xv_sc_dbg(EXEC_CHANGE, "  timeout; pl_link_config = 0x%x",
+					pl_link_config);
+				break;
+			}
+		}
+
+		xv_sc_dbg(EXEC_CHANGE, "  Change done... Checking status");
+
+		if (pl_link_config == 0xffffffff) {
+			WARN(1, "GPU fell of PCI bus!?");
+
+			/*
+			 * The rest of the driver is probably about to
+			 * explode...
+			 */
+			BUG();
+		}
+
+		link_control_status =
+			g->ops.xve.xve_readl(g, xve_link_control_status_r());
+		xv_sc_dbg(EXEC_CHANGE, "  target %d vs current %d",
+			  link_speed_setting,
+			  xve_link_control_status_link_speed_v(link_control_status));
+
+		if (err_status == -ETIMEDOUT)
+			xv_sc_dbg(EXEC_CHANGE, "  Oops timed out?");
+	} while (attempts-- > 0 &&
+		 link_speed_setting !=
+		 xve_link_control_status_link_speed_v(link_control_status));
+
+	xv_sc_dbg(EXEC_VERIF, "Verifying speed change...");
+
+	/*
+	 * Check that the new link speed is actually active. If we failed to
+	 * change to the new link speed then return to the link speed setting
+	 * pre-speed change.
+	 */
+	new_link_speed = xve_link_control_status_link_speed_v(
+		link_control_status);
+	if (link_speed_setting != new_link_speed) {
+		u32 link_config = gk20a_readl(g, xp_pl_link_config_r(0));
+
+		xv_sc_dbg(EXEC_VERIF, "  Current and target speeds mismatch!");
+		xv_sc_dbg(EXEC_VERIF, "    LINK_CONTROL_STATUS: 0x%08x",
+			  g->ops.xve.xve_readl(g, xve_link_control_status_r()));
+		xv_sc_dbg(EXEC_VERIF, "    Link speed is %s - should be %s",
+			  xve_speed_to_str(new_link_speed),
+			  xve_speed_to_str(link_speed_setting));
+
+		link_config &= ~xp_pl_link_config_max_link_rate_m();
+		if (new_link_speed ==
+		    xve_link_control_status_link_speed_link_speed_2p5_v())
+			link_config |= xp_pl_link_config_max_link_rate_f(
+				xp_pl_link_config_max_link_rate_2500_mtps_v());
+		else if (new_link_speed ==
+			 xve_link_control_status_link_speed_link_speed_5p0_v())
+			link_config |= xp_pl_link_config_max_link_rate_f(
+				xp_pl_link_config_max_link_rate_5000_mtps_v());
+		else if (new_link_speed ==
+			 xve_link_control_status_link_speed_link_speed_8p0_v())
+			link_config |= xp_pl_link_config_max_link_rate_f(
+				xp_pl_link_config_max_link_rate_8000_mtps_v());
+		else
+			link_config |= xp_pl_link_config_max_link_rate_f(
+				xp_pl_link_config_max_link_rate_2500_mtps_v());
+
+		gk20a_writel(g, xp_pl_link_config_r(0), link_config);
+		err_status = -ENODEV;
+	} else {
+		xv_sc_dbg(EXEC_VERIF, "  Current and target speeds match!");
+		err_status = 0;
+	}
+
+done:
+	/* Restore safe timings. */
+	xv_sc_dbg(CLEANUP, "Restoring saved DL settings...");
+	gk20a_writel(g, xp_dl_mgr_r(0), saved_dl_mgr);
+	xv_sc_dbg(CLEANUP, "  Done");
+
+	xv_sc_dbg(CLEANUP, "Re-enabling ASPM settings...");
+	enable_aspm_gp106(g);
+	xv_sc_dbg(CLEANUP, "  Done");
+
+	return err_status;
+}
+
+/**
+ * Sets the PCIe link speed to @xve_link_speed which must be one of:
+ *
+ *   %GPU_XVE_SPEED_2P5
+ *   %GPU_XVE_SPEED_5P0
+ *   %GPU_XVE_SPEED_8P0
+ *
+ * If an error is encountered an appropriate error will be returned.
+ */
+static int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
+{
+	u32 current_link_speed;
+	int err;
+
+	if ((next_link_speed & GPU_XVE_SPEED_MASK) == 0)
+		return -EINVAL;
+
+	err = g->ops.xve.get_speed(g, &current_link_speed);
+	if (err)
+		return err;
+
+	/* No-op. */
+	if (current_link_speed == next_link_speed)
+		return 0;
+
+	return __do_xve_set_speed_gp106(g, next_link_speed);
+}
+
+/**
+ * Places a bitmask of available speeds for gp106 in @speed_mask.
+ */
+static void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask)
+{
+	*speed_mask = GPU_XVE_SPEED_2P5 | GPU_XVE_SPEED_5P0;
+}
+
+static ssize_t xve_link_speed_write(struct file *filp,
+				    const char __user *buff,
+				    size_t len, loff_t *off)
+{
+	struct gk20a *g = ((struct seq_file *)filp->private_data)->private;
+	char kbuff[16];
+	u32 buff_size, check_len;
+	u32 link_speed = 0;
+	int ret;
+
+	buff_size = min_t(size_t, 16, len);
+
+	memset(kbuff, 0, 16);
+	if (copy_from_user(kbuff, buff, buff_size))
+		return -EFAULT;
+
+	check_len = strlen("Gen1");
+	if (strncmp(kbuff, "Gen1", check_len) == 0)
+		link_speed = GPU_XVE_SPEED_2P5;
+	else if (strncmp(kbuff, "Gen2", check_len) == 0)
+		link_speed = GPU_XVE_SPEED_5P0;
+	else if (strncmp(kbuff, "Gen3", check_len) == 0)
+		link_speed = GPU_XVE_SPEED_8P0;
+	else
+		gk20a_err(g->dev, "%s: Unknown PCIe speed: %s\n",
+			  __func__, kbuff);
+
+	if (!link_speed)
+		return -EINVAL;
+
+	/* Brief pause... To help rate limit this. */
+	msleep(250);
+
+	/*
+	 * And actually set the speed. Yay.
+	 */
+	ret = g->ops.xve.set_speed(g, link_speed);
+	if (ret)
+		return ret;
+
+	return len;
+}
+
+static int xve_link_speed_show(struct seq_file *s, void *unused)
+{
+	struct gk20a *g = s->private;
+	u32 speed;
+	int err;
+
+	err = g->ops.xve.get_speed(g, &speed);
+	if (err)
+		return err;
+
+	seq_printf(s, "Current PCIe speed:\n  %s\n", xve_speed_to_str(speed));
+
+	return 0;
+}
+
+static int xve_link_speed_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, xve_link_speed_show, inode->i_private);
+}
+
+static const struct file_operations xve_link_speed_fops = {
+	.open = xve_link_speed_open,
+	.read = seq_read,
+	.write = xve_link_speed_write,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static int xve_available_speeds_show(struct seq_file *s, void *unused)
+{
+	struct gk20a *g = s->private;
+	u32 available_speeds;
+
+	g->ops.xve.available_speeds(g, &available_speeds);
+
+	seq_puts(s, "Available PCIe bus speeds:\n");
+	if (available_speeds & GPU_XVE_SPEED_2P5)
+		seq_puts(s, "  Gen1\n");
+	if (available_speeds & GPU_XVE_SPEED_5P0)
+		seq_puts(s, "  Gen2\n");
+	if (available_speeds & GPU_XVE_SPEED_8P0)
+		seq_puts(s, "  Gen3\n");
+
+	return 0;
+}
+
+static int xve_available_speeds_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, xve_available_speeds_show, inode->i_private);
+}
+
+static const struct file_operations xve_available_speeds_fops = {
+	.open = xve_available_speeds_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static int xve_link_control_status_show(struct seq_file *s, void *unused)
+{
+	struct gk20a *g = s->private;
+	u32 link_status;
+
+	link_status = g->ops.xve.xve_readl(g, xve_link_control_status_r());
+	seq_printf(s, "0x%08x\n", link_status);
+
+	return 0;
+}
+
+static int xve_link_control_status_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, xve_link_control_status_show, inode->i_private);
+}
+
+static const struct file_operations xve_link_control_status_fops = {
+	.open = xve_link_control_status_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static int xve_sw_init_gp106(struct device *dev)
+{
+	int err = -ENODEV;
+#ifdef CONFIG_DEBUG_FS
+	struct gk20a *g = get_gk20a(dev);
+	struct gk20a_platform *plat = gk20a_get_platform(dev);
+	struct dentry *gpu_root = plat->debugfs;
+
+	g->debugfs_xve = debugfs_create_dir("xve", gpu_root);
+	if (IS_ERR_OR_NULL(g->debugfs_xve))
+		goto fail;
+
+	/*
+	 * These are just debug nodes. If they fail to get made it's not worth
+	 * worrying the higher level SW.
+	 */
+	debugfs_create_file("link_speed", S_IRUGO,
+			    g->debugfs_xve, g,
+			    &xve_link_speed_fops);
+	debugfs_create_file("available_speeds", S_IRUGO,
+			    g->debugfs_xve, g,
+			    &xve_available_speeds_fops);
+	debugfs_create_file("link_control_status", S_IRUGO,
+			    g->debugfs_xve, g,
+			    &xve_link_control_status_fops);
+
+	err = 0;
+fail:
+	return err;
+#else
+	return err;
+#endif
+}
+
+/*
+ * Init the HAL functions and what not. xve_sw_init_gp106() is for initializing
+ * all the other stuff like debugfs nodes, etc.
+ */
+int gp106_init_xve_ops(struct gpu_ops *gops)
+{
+	gops->xve.sw_init          = xve_sw_init_gp106;
+	gops->xve.get_speed        = xve_get_speed_gp106;
+	gops->xve.set_speed        = xve_set_speed_gp106;
+	gops->xve.available_speeds = xve_available_speeds_gp106;
+	gops->xve.xve_readl        = xve_xve_readl_gp106;
+	gops->xve.xve_writel       = xve_xve_writel_gp106;
+
+	return 0;
+}

drivers/gpu/nvgpu/gp106/xve_gp106.h

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __XVE_GP106_H__
+#define __XVE_GP106_H__
+
+#include "gk20a/gk20a.h"
+
+int gp106_init_xve_ops(struct gpu_ops *gops);
+
+/*
+ * Best guess for a reasonable timeout.
+ */
+#define GPU_XVE_TIMEOUT_MS	500
+
+/*
+ * For the available speeds bitmap.
+ */
+#define GPU_XVE_SPEED_2P5	(1 << 0)
+#define GPU_XVE_SPEED_5P0	(1 << 1)
+#define GPU_XVE_SPEED_8P0	(1 << 2)
+#define GPU_XVE_NR_SPEEDS	3
+
+#define GPU_XVE_SPEED_MASK	(GPU_XVE_SPEED_2P5 |	\
+				 GPU_XVE_SPEED_5P0 |	\
+				 GPU_XVE_SPEED_8P0)
+
+/*
+ * The HW uses a 2 bit field where speed is defined by a number:
+ *
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3
+ *
+ * This isn't ideal for a bitmap with available speeds. So the external
+ * APIs think about speeds as a bit in a bitmap and this function converts
+ * from those bits to the actual HW speed setting.
+ *
+ * @speed_bit must have only 1 bit set and must be one of the 3 available
+ * HW speeds. Not all chips support all speeds so use available_speeds() to
+ * determine what a given chip supports.
+ */
+static inline u32 xve_speed_to_hw_speed_setting(u32 speed_bit)
+{
+	if (!speed_bit ||
+	    !is_power_of_2(speed_bit) ||
+	    !(speed_bit & GPU_XVE_SPEED_MASK))
+		return -EINVAL;
+
+	return ilog2(speed_bit) + 1;
+}
+
+static inline const char *xve_speed_to_str(u32 speed)
+{
+	if (!speed || !is_power_of_2(speed) ||
+	    !(speed & GPU_XVE_SPEED_MASK))
+		return "Unknown ???";
+
+	return speed & GPU_XVE_SPEED_2P5 ? "Gen1" :
+	       speed & GPU_XVE_SPEED_5P0 ? "Gen2" :
+	       speed & GPU_XVE_SPEED_8P0 ? "Gen3" :
+	       "Unknown ???";
+}
+
+/*
+ * Debugging for the speed change.
+ */
+enum xv_speed_change_steps {
+	PRE_CHANGE = 0,
+	DISABLE_ASPM,
+	DL_SAFE_MODE,
+	CHECK_LINK,
+	LINK_SETTINGS,
+	EXEC_CHANGE,
+	EXEC_VERIF,
+	CLEANUP
+};
+
+#define xv_dbg(fmt, args...)			\
+	gk20a_dbg(gpu_dbg_xv, fmt, ##args)
+
+#define xv_sc_dbg(step, fmt, args...)					\
+	xv_dbg("[%d] %15s | " fmt, step, __stringify(step), ##args)
+
+
+#endif

drivers/gpu/nvgpu/gp10b/cde_gp10b.c

@@ -0,0 +1,148 @@
+/*
+ * GP10B CDE
+ *
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "cde_gp10b.h"
+
+enum gp10b_programs {
+	GP10B_PROG_HPASS              = 0,
+	GP10B_PROG_HPASS_4K           = 1,
+	GP10B_PROG_VPASS              = 2,
+	GP10B_PROG_VPASS_4K           = 3,
+	GP10B_PROG_HPASS_DEBUG        = 4,
+	GP10B_PROG_HPASS_4K_DEBUG     = 5,
+	GP10B_PROG_VPASS_DEBUG        = 6,
+	GP10B_PROG_VPASS_4K_DEBUG     = 7,
+	GP10B_PROG_PASSTHROUGH        = 8,
+};
+
+static void gp10b_cde_get_program_numbers(struct gk20a *g,
+					  u32 block_height_log2,
+					  int *hprog_out, int *vprog_out)
+{
+	int hprog, vprog;
+
+	if (g->cde_app.shader_parameter == 1) {
+		hprog = GP10B_PROG_PASSTHROUGH;
+		vprog = GP10B_PROG_PASSTHROUGH;
+	} else {
+		hprog = GP10B_PROG_HPASS;
+		vprog = GP10B_PROG_VPASS;
+		if (g->cde_app.shader_parameter == 2) {
+			hprog = GP10B_PROG_HPASS_DEBUG;
+			vprog = GP10B_PROG_VPASS_DEBUG;
+		}
+		if (g->mm.bypass_smmu) {
+			if (!g->mm.disable_bigpage) {
+				gk20a_warn(g->dev,
+					   "when bypass_smmu is 1, disable_bigpage must be 1 too");
+			}
+			hprog |= 1;
+			vprog |= 1;
+		}
+	}
+
+	*hprog_out = hprog;
+	*vprog_out = vprog;
+}
+
+static bool gp10b_need_scatter_buffer(struct gk20a *g)
+{
+	return g->mm.bypass_smmu;
+}
+
+static u8 parity(u32 a)
+{
+	a ^= a>>16u;
+	a ^= a>>8u;
+	a ^= a>>4u;
+	a &= 0xfu;
+	return (0x6996u >> a) & 1u;
+}
+
+static int gp10b_populate_scatter_buffer(struct gk20a *g,
+					 struct sg_table *sgt,
+					 size_t surface_size,
+					 void *scatter_buffer_ptr,
+					 size_t scatter_buffer_size)
+{
+	/* map scatter buffer to CPU VA and fill it */
+	const u32 page_size_log2 = 12;
+	const u32 page_size = 1 << page_size_log2;
+	const u32 page_size_shift = page_size_log2 - 7u;
+
+	/* 0011 1111 1111 1111 1111 1110 0100 1000 */
+	const u32 getSliceMaskGP10B = 0x3ffffe48;
+	u8 *scatter_buffer = scatter_buffer_ptr;
+
+	size_t i;
+	struct scatterlist *sg = NULL;
+	u8 d = 0;
+	size_t page = 0;
+	size_t pages_left;
+
+	surface_size = round_up(surface_size, page_size);
+
+	pages_left = surface_size >> page_size_log2;
+	if ((pages_left >> 3) > scatter_buffer_size)
+	    return -ENOMEM;
+
+	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+		unsigned int j;
+		u64 surf_pa = sg_phys(sg);
+		unsigned int n = (int)(sg->length >> page_size_log2);
+
+		gk20a_dbg(gpu_dbg_cde, "surfPA=0x%llx + %d pages", surf_pa, n);
+
+		for (j=0; j < n && pages_left > 0; j++, surf_pa += page_size) {
+			u32 addr = (((u32)(surf_pa>>7)) & getSliceMaskGP10B) >> page_size_shift;
+			u8 scatter_bit = parity(addr);
+			u8 bit = page & 7;
+
+			d |= scatter_bit << bit;
+			if (bit == 7) {
+				scatter_buffer[page >> 3] = d;
+				d = 0;
+			}
+
+			++page;
+			--pages_left;
+		}
+
+		if (pages_left == 0)
+			break;
+	}
+
+	/* write the last byte in case the number of pages is not divisible by 8 */
+	if ((page & 7) != 0)
+		scatter_buffer[page >> 3] = d;
+
+#if defined(GK20A_DEBUG)
+	if (unlikely(gpu_dbg_cde & gk20a_dbg_mask)) {
+		gk20a_dbg(gpu_dbg_cde, "scatterBuffer content:");
+		for (i=0; i < page>>3; i++) {
+			gk20a_dbg(gpu_dbg_cde, " %x", scatter_buffer[i]);
+		}
+	}
+#endif
+	return 0;
+}
+
+void gp10b_init_cde_ops(struct gpu_ops *gops)
+{
+	gops->cde.get_program_numbers = gp10b_cde_get_program_numbers;
+	gops->cde.need_scatter_buffer = gp10b_need_scatter_buffer;
+	gops->cde.populate_scatter_buffer = gp10b_populate_scatter_buffer;
+}

drivers/gpu/nvgpu/gp10b/cde_gp10b.h

@@ -0,0 +1,23 @@
+/*
+ * GP10B CDE
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVHOST_GP10B_CDE
+#define _NVHOST_GP10B_CDE
+
+struct gpu_ops;
+
+void gp10b_init_cde_ops(struct gpu_ops *gops);
+
+#endif

drivers/gpu/nvgpu/gp10b/ce_gp10b.c

@@ -0,0 +1,82 @@
+/*
+ * Pascal GPU series Copy Engine.
+ *
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.
+ */
+
+#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
+#include "hw_ce_gp10b.h"
+#include "ce_gp10b.h"
+
+static void ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
+{
+	gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n");
+
+	/* wake theads waiting in this channel */
+	gk20a_channel_semaphore_wakeup(g, true);
+	return;
+}
+
+static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
+{
+	gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n");
+
+	return ce_intr_status_blockpipe_pending_f();
+}
+
+static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr)
+{
+	gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n");
+
+	return ce_intr_status_launcherr_pending_f();
+}
+
+static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+{
+	u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
+	u32 clear_intr = 0;
+
+	gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
+
+	/* clear blocking interrupts: they exibit broken behavior */
+	if (ce_intr & ce_intr_status_blockpipe_pending_f())
+		clear_intr |= ce_blockpipe_isr(g, ce_intr);
+
+	if (ce_intr & ce_intr_status_launcherr_pending_f())
+		clear_intr |= ce_launcherr_isr(g, ce_intr);
+
+	gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
+	return;
+}
+
+static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+{
+	u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
+
+	gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
+
+	if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) {
+		gk20a_writel(g, ce_intr_status_r(inst_id),
+			ce_intr_status_nonblockpipe_pending_f());
+		ce_nonblockpipe_isr(g, ce_intr);
+	}
+
+	return;
+}
+void gp10b_init_ce(struct gpu_ops *gops)
+{
+	gops->ce2.isr_stall = gp10b_ce_isr;
+	gops->ce2.isr_nonstall = gp10b_ce_nonstall_isr;
+}

drivers/gpu/nvgpu/gp10b/ce_gp10b.h

@@ -0,0 +1,26 @@
+/*
+ * Pascal GPU series Copy Engine.
+ *
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.
+ */
+#ifndef __CE_GP10B_H__
+#define __CE_GP10B_H__
+
+#include "gk20a/channel_gk20a.h"
+#include "gk20a/tsg_gk20a.h"
+
+void gp10b_init_ce(struct gpu_ops *gops);
+
+#endif /*__CE2_GP10B_H__*/

drivers/gpu/nvgpu/gp10b/fb_gp10b.c

@@ -0,0 +1,108 @@
+/*
+ * GP10B FB
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+#include "gm20b/fb_gm20b.h"
+#include "gk20a/kind_gk20a.h"
+
+#include "hw_gmmu_gp10b.h"
+
+static void gp10b_init_uncompressed_kind_map(void)
+{
+	gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] =
+	gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] =
+	gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] =
+	gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] =
+	gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] =
+		gmmu_pte_kind_z16_v();
+
+	gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] =
+	gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] =
+		gmmu_pte_kind_generic_16bx2_v();
+}
+
+static bool gp10b_kind_supported(u8 k)
+{
+	return (k >= gmmu_pte_kind_z16_2cz_v() &&
+		k <= gmmu_pte_kind_z16_ms8_2cz_v())
+		|| k == gmmu_pte_kind_z16_ms16_2cz_v()
+		|| k == gmmu_pte_kind_c32_ms4_4cbra_v()
+		|| k == gmmu_pte_kind_c64_ms4_4cbra_v();
+}
+
+static bool gp10b_kind_z(u8 k)
+{
+	return (k >= gmmu_pte_kind_z16_2cz_v() &&
+		 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
+		k == gmmu_pte_kind_z16_ms16_2cz_v();
+}
+
+static bool gp10b_kind_compressible(u8 k)
+{
+	return (k >= gmmu_pte_kind_z16_2cz_v() &&
+		 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
+		k == gmmu_pte_kind_z16_ms16_2cz_v() ||
+	       (k >= gmmu_pte_kind_z16_4cz_v() &&
+		 k <= gmmu_pte_kind_z16_ms16_4cz_v()) ||
+		k == gmmu_pte_kind_c32_ms4_4cbra_v() ||
+		k == gmmu_pte_kind_c64_ms4_4cbra_v();
+}
+
+static bool gp10b_kind_zbc(u8 k)
+{
+	return (k >= gmmu_pte_kind_z16_2cz_v() &&
+		 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
+		k == gmmu_pte_kind_z16_ms16_2cz_v() ||
+		k == gmmu_pte_kind_c32_ms4_4cbra_v() ||
+		k == gmmu_pte_kind_c64_ms4_4cbra_v();
+}
+
+static void gp10b_init_kind_attr(void)
+{
+	u16 k;
+
+	for (k = 0; k < 256; k++) {
+		if (gp10b_kind_supported((u8)k))
+			gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED;
+		if (gp10b_kind_compressible((u8)k))
+			gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE;
+		if (gp10b_kind_z((u8)k))
+			gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z;
+		if (gp10b_kind_zbc((u8)k))
+			gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC;
+	}
+}
+
+static unsigned int gp10b_fb_compression_page_size(struct gk20a *g)
+{
+	return SZ_64K;
+}
+
+static unsigned int gp10b_fb_compressible_page_size(struct gk20a *g)
+{
+	return SZ_4K;
+}
+
+void gp10b_init_fb(struct gpu_ops *gops)
+{
+	gm20b_init_fb(gops);
+	gops->fb.compression_page_size = gp10b_fb_compression_page_size;
+	gops->fb.compressible_page_size = gp10b_fb_compressible_page_size;
+
+	gp10b_init_uncompressed_kind_map();
+	gp10b_init_kind_attr();
+}

drivers/gpu/nvgpu/gp10b/fb_gp10b.h

@@ -0,0 +1,21 @@
+/*
+ * GP10B FB
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_GP10B_FB
+#define _NVGPU_GP10B_FB
+struct gpu_ops;
+
+void gp10b_init_fb(struct gpu_ops *gops);
+#endif

drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c

@@ -0,0 +1,53 @@
+/*
+ * GP10B GPU FECS traces
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gk20a/fecs_trace_gk20a.h"
+#include "gp10b/hw_ctxsw_prog_gp10b.h"
+#include "gp10b/hw_gr_gp10b.h"
+
+#ifdef CONFIG_GK20A_CTXSW_TRACE
+static int gp10b_fecs_trace_flush(struct gk20a *g)
+{
+	struct fecs_method_op_gk20a op = {
+		.mailbox = { .id = 0, .data = 0,
+			.clr = ~0, .ok = 0, .fail = 0},
+		.method.addr = gr_fecs_method_push_adr_write_timestamp_record_v(),
+		.method.data = 0,
+		.cond.ok = GR_IS_UCODE_OP_NOT_EQUAL,
+		.cond.fail = GR_IS_UCODE_OP_SKIP,
+	};
+	int err;
+
+	gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "");
+
+	err = gr_gk20a_elpg_protected_call(g,
+			gr_gk20a_submit_fecs_method_op(g, op, false));
+	if (err)
+		gk20a_err(dev_from_gk20a(g), "write timestamp record failed");
+
+	return err;
+}
+
+void gp10b_init_fecs_trace_ops(struct gpu_ops *ops)
+{
+	gk20a_init_fecs_trace_ops(ops);
+	ops->fecs_trace.flush = gp10b_fecs_trace_flush;
+}
+#else
+void gp10b_init_fecs_trace_ops(struct gpu_ops *ops)
+{
+}
+#endif /* CONFIG_GK20A_CTXSW_TRACE */

drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h

@@ -0,0 +1,23 @@
+/*
+ * GP10B GPU FECS traces
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_FECS_TRACE_GP10B_H_
+#define _NVGPU_FECS_TRACE_GP10B_H_
+
+struct gpu_ops;
+
+int gp10b_init_fecs_trace_ops(struct gpu_ops *);
+
+#endif

drivers/gpu/nvgpu/gp10b/fifo_gp10b.c

@@ -0,0 +1,238 @@
+/*
+ * GP10B fifo
+ *
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+#include "gm20b/fifo_gm20b.h"
+#include "hw_pbdma_gp10b.h"
+#include "fifo_gp10b.h"
+#include "hw_ccsr_gp10b.h"
+#include "hw_fifo_gp10b.h"
+#include "hw_ram_gp10b.h"
+#include "hw_top_gp10b.h"
+
+static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g,
+				struct mem_desc *mem)
+{
+	u32 val;
+
+	gk20a_dbg_fn("");
+
+	val = gk20a_mem_rd32(g, mem,
+			ram_in_page_dir_base_fault_replay_tex_w());
+	val &= ~ram_in_page_dir_base_fault_replay_tex_m();
+	val |= ram_in_page_dir_base_fault_replay_tex_true_f();
+	gk20a_mem_wr32(g, mem,
+		ram_in_page_dir_base_fault_replay_tex_w(), val);
+
+	val = gk20a_mem_rd32(g, mem,
+			ram_in_page_dir_base_fault_replay_gcc_w());
+	val &= ~ram_in_page_dir_base_fault_replay_gcc_m();
+	val |= ram_in_page_dir_base_fault_replay_gcc_true_f();
+	gk20a_mem_wr32(g, mem,
+		ram_in_page_dir_base_fault_replay_gcc_w(), val);
+
+	gk20a_dbg_fn("done");
+}
+
+int channel_gp10b_commit_userd(struct channel_gk20a *c)
+{
+	u32 addr_lo;
+	u32 addr_hi;
+	struct gk20a *g = c->g;
+
+	gk20a_dbg_fn("");
+
+	addr_lo = u64_lo32(c->userd_iova >> ram_userd_base_shift_v());
+	addr_hi = u64_hi32(c->userd_iova);
+
+	gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx",
+		c->hw_chid, (u64)c->userd_iova);
+
+	gk20a_mem_wr32(g, &c->inst_block,
+		       ram_in_ramfc_w() + ram_fc_userd_w(),
+		       (g->mm.vidmem_is_vidmem ?
+			pbdma_userd_target_sys_mem_ncoh_f() :
+			pbdma_userd_target_vid_mem_f()) |
+		       pbdma_userd_addr_f(addr_lo));
+
+	gk20a_mem_wr32(g, &c->inst_block,
+		       ram_in_ramfc_w() + ram_fc_userd_hi_w(),
+		       pbdma_userd_hi_addr_f(addr_hi));
+
+	return 0;
+}
+
+static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
+			u64 gpfifo_base, u32 gpfifo_entries, u32 flags)
+{
+	struct gk20a *g = c->g;
+	struct mem_desc *mem = &c->inst_block;
+
+	gk20a_dbg_fn("");
+
+	gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v());
+
+	gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(),
+		pbdma_gp_base_offset_f(
+		u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
+
+	gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
+		pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
+		pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
+
+	gk20a_mem_wr32(g, mem, ram_fc_signature_w(),
+		 c->g->ops.fifo.get_pbdma_signature(c->g));
+
+	gk20a_mem_wr32(g, mem, ram_fc_formats_w(),
+		pbdma_formats_gp_fermi0_f() |
+		pbdma_formats_pb_fermi1_f() |
+		pbdma_formats_mp_fermi0_f());
+
+	gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(),
+		pbdma_pb_header_priv_user_f() |
+		pbdma_pb_header_method_zero_f() |
+		pbdma_pb_header_subchannel_zero_f() |
+		pbdma_pb_header_level_main_f() |
+		pbdma_pb_header_first_true_f() |
+		pbdma_pb_header_type_inc_f());
+
+	gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(),
+		pbdma_subdevice_id_f(1) |
+		pbdma_subdevice_status_active_f() |
+		pbdma_subdevice_channel_dma_enable_f());
+
+	gk20a_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f());
+
+	gk20a_mem_wr32(g, mem, ram_fc_acquire_w(),
+		channel_gk20a_pbdma_acquire_val(c));
+
+	gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
+		pbdma_runlist_timeslice_timeout_128_f() |
+		pbdma_runlist_timeslice_timescale_3_f() |
+		pbdma_runlist_timeslice_enable_true_f());
+
+	if ( flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE)
+		gp10b_set_pdb_fault_replay_flags(c->g, mem);
+
+
+	gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
+
+	if (c->is_privileged_channel) {
+		/* Set privilege level for channel */
+		gk20a_mem_wr32(g, mem, ram_fc_config_w(),
+			pbdma_config_auth_level_privileged_f());
+
+		gk20a_channel_setup_ramfc_for_privileged_channel(c);
+	}
+
+	return channel_gp10b_commit_userd(c);
+}
+
+static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g)
+{
+	return g->gpu_characteristics.gpfifo_class 
+		| pbdma_signature_sw_zero_f();
+}
+
+static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
+{
+	u32 new_syncpt = 0, old_syncpt;
+	u32 v;
+
+	gk20a_dbg_fn("");
+
+	v = gk20a_mem_rd32(c->g, &c->inst_block,
+			ram_fc_allowed_syncpoints_w());
+	old_syncpt = pbdma_allowed_syncpoints_0_index_v(v);
+	if (c->sync)
+		new_syncpt = c->sync->syncpt_id(c->sync);
+
+	if (new_syncpt && new_syncpt != old_syncpt) {
+		/* disable channel */
+		gk20a_disable_channel_tsg(c->g, c);
+
+		/* preempt the channel */
+		WARN_ON(gk20a_fifo_preempt(c->g, c));
+
+		v = pbdma_allowed_syncpoints_0_valid_f(1);
+
+		gk20a_dbg_info("Channel %d, syncpt id %d\n",
+				c->hw_chid, new_syncpt);
+
+		v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt);
+
+		gk20a_mem_wr32(c->g, &c->inst_block,
+				ram_fc_allowed_syncpoints_w(), v);
+	}
+
+	/* enable channel */
+	gk20a_enable_channel_tsg(c->g, c);
+
+	gk20a_dbg_fn("done");
+
+	return 0;
+}
+
+static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
+					u32 *inst_id)
+{
+	int ret = ENGINE_INVAL_GK20A;
+
+	gk20a_dbg_info("engine type %d", engine_type);
+	if (engine_type == top_device_info_type_enum_graphics_v())
+		ret = ENGINE_GR_GK20A;
+	else if (engine_type == top_device_info_type_enum_lce_v()) {
+		/* Default assumptions - all the CE engine have separate runlist */
+		ret = ENGINE_ASYNC_CE_GK20A;
+	}
+
+	return ret;
+}
+
+static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
+				u32 *inst_id, u32 *pri_base, u32 *fault_id)
+{
+	if (top_device_info_data_type_v(table_entry) ==
+	    top_device_info_data_type_enum2_v()) {
+		if (inst_id)
+			*inst_id = top_device_info_data_inst_id_v(table_entry);
+		if (pri_base) {
+			*pri_base =
+			    (top_device_info_data_pri_base_v(table_entry)
+			    << top_device_info_data_pri_base_align_v());
+		}
+		if (fault_id && (top_device_info_data_fault_id_v(table_entry) ==
+		    top_device_info_data_fault_id_valid_v())) {
+			*fault_id =
+			     top_device_info_data_fault_id_enum_v(table_entry);
+		}
+	} else
+		gk20a_err(g->dev, "unknown device_info_data %d",
+			top_device_info_data_type_v(table_entry));
+}
+
+void gp10b_init_fifo(struct gpu_ops *gops)
+{
+	gm20b_init_fifo(gops);
+	gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc;
+	gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature;
+	gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
+	gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
+	gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
+	gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
+}

drivers/gpu/nvgpu/gp10b/fifo_gp10b.h

@@ -0,0 +1,21 @@
+/*
+ * GP10B Fifo
+ *
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef FIFO_GP10B_H
+#define FIFO_GP10B_H
+struct gpu_ops;
+void gp10b_init_fifo(struct gpu_ops *gops);
+int channel_gp10b_commit_userd(struct channel_gk20a *c);
+#endif

drivers/gpu/nvgpu/gp10b/gp10b.c

@@ -0,0 +1,110 @@
+/*
+ * GP10B Graphics
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "gk20a/gk20a.h"
+#include "hw_fuse_gp10b.h"
+#include "hw_gr_gp10b.h"
+
+static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
+{
+	u64 ecc_enabled_units = 0;
+	u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
+	u32 opt_feature_fuses_override_disable =
+			gk20a_readl(g,
+				fuse_opt_feature_fuses_override_disable_r());
+	u32 fecs_feature_override_ecc =
+				gk20a_readl(g,
+					gr_fecs_feature_override_ecc_r());
+
+	if (opt_feature_fuses_override_disable) {
+		if (opt_ecc_en)
+			ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED;
+		else
+			ecc_enabled_units = 0;
+	} else {
+		/* SM LRF */
+		if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
+						fecs_feature_override_ecc)) {
+			if (gr_fecs_feature_override_ecc_sm_lrf_v(
+						fecs_feature_override_ecc)) {
+				ecc_enabled_units |=
+					NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
+			}
+		} else {
+			if (opt_ecc_en) {
+				ecc_enabled_units |=
+					NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
+			}
+		}
+
+		/* SM SHM */
+		if (gr_fecs_feature_override_ecc_sm_shm_override_v(
+						fecs_feature_override_ecc)) {
+			if (gr_fecs_feature_override_ecc_sm_shm_v(
+						fecs_feature_override_ecc)) {
+				ecc_enabled_units |=
+					NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
+			}
+		} else {
+			if (opt_ecc_en) {
+				ecc_enabled_units |=
+					NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
+			}
+		}
+
+		/* TEX */
+		if (gr_fecs_feature_override_ecc_tex_override_v(
+						fecs_feature_override_ecc)) {
+			if (gr_fecs_feature_override_ecc_tex_v(
+						fecs_feature_override_ecc)) {
+				ecc_enabled_units |=
+					NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
+			}
+		} else {
+			if (opt_ecc_en) {
+				ecc_enabled_units |=
+					NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
+			}
+		}
+
+		/* LTC */
+		if (gr_fecs_feature_override_ecc_ltc_override_v(
+						fecs_feature_override_ecc)) {
+			if (gr_fecs_feature_override_ecc_ltc_v(
+						fecs_feature_override_ecc)) {
+				ecc_enabled_units |=
+					NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
+			}
+		} else {
+			if (opt_ecc_en) {
+				ecc_enabled_units |=
+					NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
+			}
+		}
+	}
+
+	return ecc_enabled_units;
+}
+
+int gp10b_init_gpu_characteristics(struct gk20a *g)
+{
+	gk20a_init_gpu_characteristics(g);
+	g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g);
+
+	return 0;
+}

drivers/gpu/nvgpu/gp10b/gp10b.h

@@ -0,0 +1,26 @@
+/*
+ * GP10B Graphics
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef GP10B_H
+#define GP10B_H
+
+#include "gk20a/gk20a.h"
+
+int gp10b_init_gpu_characteristics(struct gk20a *g);
+
+#endif /* GP10B_H */

drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c

@@ -0,0 +1,640 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#ifndef __gp10b_gating_reglist_h__
+#define __gp10b_gating_reglist_h__
+
+#include <linux/types.h>
+#include "gp10b_gating_reglist.h"
+
+struct gating_desc {
+	u32 addr;
+	u32 prod;
+	u32 disable;
+};
+/* slcg bus */
+static const struct gating_desc gp10b_slcg_bus[] = {
+	{.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
+};
+
+/* slcg ce2 */
+static const struct gating_desc gp10b_slcg_ce2[] = {
+	{.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
+};
+
+/* slcg chiplet */
+static const struct gating_desc gp10b_slcg_chiplet[] = {
+	{.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
+	{.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
+};
+
+/* slcg fb */
+static const struct gating_desc gp10b_slcg_fb[] = {
+	{.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
+};
+
+/* slcg fifo */
+static const struct gating_desc gp10b_slcg_fifo[] = {
+	{.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe},
+};
+
+/* slcg gr */
+static const struct gating_desc gp10b_slcg_gr[] = {
+	{.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe},
+	{.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
+	{.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
+	{.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
+	{.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
+	{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
+	{.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
+	{.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
+	{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
+	{.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e},
+	{.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
+	{.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe},
+	{.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe},
+	{.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
+	{.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
+	{.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
+	{.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
+	{.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
+	{.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
+	{.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
+	{.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
+	{.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
+	{.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
+	{.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
+	{.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
+	{.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
+	{.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
+	{.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
+	{.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
+	{.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
+	{.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
+	{.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
+	{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
+	{.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
+	{.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
+};
+
+/* slcg ltc */
+static const struct gating_desc gp10b_slcg_ltc[] = {
+	{.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
+	{.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
+};
+
+/* slcg perf */
+static const struct gating_desc gp10b_slcg_perf[] = {
+	{.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
+	{.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
+};
+
+/* slcg PriRing */
+static const struct gating_desc gp10b_slcg_priring[] = {
+	{.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
+};
+
+/* slcg pwr_csb */
+static const struct gating_desc gp10b_slcg_pwr_csb[] = {
+	{.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe},
+	{.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
+	{.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe},
+	{.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* slcg pmu */
+static const struct gating_desc gp10b_slcg_pmu[] = {
+	{.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
+	{.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe},
+	{.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* therm gr */
+static const struct gating_desc gp10b_slcg_therm[] = {
+	{.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* slcg Xbar */
+static const struct gating_desc gp10b_slcg_xbar[] = {
+	{.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
+	{.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
+};
+
+/* blcg bus */
+static const struct gating_desc gp10b_blcg_bus[] = {
+	{.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
+};
+
+/* blcg ce */
+static const struct gating_desc gp10b_blcg_ce[] = {
+	{.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000},
+};
+
+/* blcg ctxsw prog */
+static const struct gating_desc gp10b_blcg_ctxsw_prog[] = {
+};
+
+/* blcg fb */
+static const struct gating_desc gp10b_blcg_fb[] = {
+	{.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
+	{.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
+};
+
+/* blcg fifo */
+static const struct gating_desc gp10b_blcg_fifo[] = {
+	{.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg gr */
+static const struct gating_desc gp10b_blcg_gr[] = {
+	{.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
+	{.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
+	{.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
+	{.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
+	{.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
+	{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
+	{.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
+	{.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
+	{.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
+	{.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
+	{.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
+	{.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
+	{.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
+	{.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
+	{.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
+	{.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
+	{.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
+	{.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
+	{.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
+	{.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
+	{.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
+	{.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
+	{.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
+	{.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
+	{.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg ltc */
+static const struct gating_desc gp10b_blcg_ltc[] = {
+	{.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
+	{.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
+};
+
+/* blcg pwr_csb  */
+static const struct gating_desc gp10b_blcg_pwr_csb[] = {
+	{.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
+};
+
+/* blcg pmu */
+static const struct gating_desc gp10b_blcg_pmu[] = {
+	{.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
+};
+
+/* blcg Xbar */
+static const struct gating_desc gp10b_blcg_xbar[] = {
+	{.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
+	{.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
+};
+
+/* pg gr */
+static const struct gating_desc gp10b_pg_gr[] = {
+};
+
+/* inline functions */
+void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_bus[i].addr,
+				gp10b_slcg_bus[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_bus[i].addr,
+				 gp10b_slcg_bus[i].disable);
+	}
+}
+
+void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_ce2[i].addr,
+				gp10b_slcg_ce2[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_ce2[i].addr,
+				 gp10b_slcg_ce2[i].disable);
+	}
+}
+
+void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
+				gp10b_slcg_chiplet[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
+				 gp10b_slcg_chiplet[i].disable);
+	}
+}
+
+void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+}
+
+void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_fb[i].addr,
+				gp10b_slcg_fb[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_fb[i].addr,
+				 gp10b_slcg_fb[i].disable);
+	}
+}
+
+void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_fifo[i].addr,
+				gp10b_slcg_fifo[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_fifo[i].addr,
+				 gp10b_slcg_fifo[i].disable);
+	}
+}
+
+void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_gr[i].addr,
+				gp10b_slcg_gr[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_gr[i].addr,
+				 gp10b_slcg_gr[i].disable);
+	}
+}
+
+void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_ltc[i].addr,
+				gp10b_slcg_ltc[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_ltc[i].addr,
+				gp10b_slcg_ltc[i].disable);
+	}
+}
+
+void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_perf[i].addr,
+				gp10b_slcg_perf[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_perf[i].addr,
+				gp10b_slcg_perf[i].disable);
+	}
+}
+
+void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_priring[i].addr,
+				gp10b_slcg_priring[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_priring[i].addr,
+				gp10b_slcg_priring[i].disable);
+	}
+}
+
+void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
+				gp10b_slcg_pwr_csb[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
+				gp10b_slcg_pwr_csb[i].disable);
+	}
+}
+
+void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_pmu[i].addr,
+				gp10b_slcg_pmu[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_pmu[i].addr,
+				gp10b_slcg_pmu[i].disable);
+	}
+}
+
+void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_therm[i].addr,
+				gp10b_slcg_therm[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_therm[i].addr,
+				gp10b_slcg_therm[i].disable);
+	}
+}
+
+void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_slcg_xbar[i].addr,
+				gp10b_slcg_xbar[i].prod);
+		else
+			gk20a_writel(g, gp10b_slcg_xbar[i].addr,
+				gp10b_slcg_xbar[i].disable);
+	}
+}
+
+void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_bus[i].addr,
+				gp10b_blcg_bus[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_bus[i].addr,
+				gp10b_blcg_bus[i].disable);
+	}
+}
+
+void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_ce[i].addr,
+				gp10b_blcg_ce[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_ce[i].addr,
+				gp10b_blcg_ce[i].disable);
+	}
+}
+
+void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
+				gp10b_blcg_ctxsw_prog[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
+				gp10b_blcg_ctxsw_prog[i].disable);
+	}
+}
+
+void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_fb[i].addr,
+				gp10b_blcg_fb[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_fb[i].addr,
+				gp10b_blcg_fb[i].disable);
+	}
+}
+
+void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_fifo[i].addr,
+				gp10b_blcg_fifo[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_fifo[i].addr,
+				gp10b_blcg_fifo[i].disable);
+	}
+}
+
+void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_gr[i].addr,
+				gp10b_blcg_gr[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_gr[i].addr,
+				gp10b_blcg_gr[i].disable);
+	}
+}
+
+void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_ltc[i].addr,
+				gp10b_blcg_ltc[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_ltc[i].addr,
+				gp10b_blcg_ltc[i].disable);
+	}
+}
+
+void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
+				gp10b_blcg_pwr_csb[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
+				gp10b_blcg_pwr_csb[i].disable);
+	}
+}
+
+void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_pmu[i].addr,
+				gp10b_blcg_pmu[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_pmu[i].addr,
+				gp10b_blcg_pmu[i].disable);
+	}
+}
+
+void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_blcg_xbar[i].addr,
+				gp10b_blcg_xbar[i].prod);
+		else
+			gk20a_writel(g, gp10b_blcg_xbar[i].addr,
+				gp10b_blcg_xbar[i].disable);
+	}
+}
+
+void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
+	bool prod)
+{
+	u32 i;
+	u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc);
+	for (i = 0; i < size; i++) {
+		if (prod)
+			gk20a_writel(g, gp10b_pg_gr[i].addr,
+				gp10b_pg_gr[i].prod);
+		else
+			gk20a_writel(g, gp10b_pg_gr[i].addr,
+				gp10b_pg_gr[i].disable);
+	}
+}
+
+#endif /* __gp10b_gating_reglist_h__ */

drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "gk20a/gk20a.h"
+
+void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
+	bool prod);
+
+void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
+	bool prod);
+

drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c

@@ -0,0 +1,64 @@
+/*
+ * GP10B specific sysfs files
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/platform_device.h>
+
+#include "gk20a/gk20a.h"
+#include "gp10b_sysfs.h"
+
+#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH)
+
+static ssize_t ecc_enable_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct gk20a *g = get_gk20a(dev);
+	u32 ecc_mask;
+	u32 err = 0;
+
+	err = sscanf(buf, "%d", &ecc_mask);
+	if (err == 1) {
+		err = g->ops.pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd
+			(g, ecc_mask);
+		if (err)
+			dev_err(dev, "ECC override did not happen\n");
+	} else
+		return -EINVAL;
+	return count;
+}
+
+static ssize_t ecc_enable_read(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct gk20a *g = get_gk20a(dev);
+
+	return sprintf(buf, "ecc override =0x%x\n",
+			g->ops.gr.get_lrf_tex_ltc_dram_override(g));
+}
+
+static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store);
+
+void gp10b_create_sysfs(struct device *dev)
+{
+	int error = 0;
+
+	error |= device_create_file(dev, &dev_attr_ecc_enable);
+	if (error)
+		dev_err(dev, "Failed to create sysfs attributes!\n");
+}
+
+void gp10b_remove_sysfs(struct device *dev)
+{
+	device_remove_file(dev, &dev_attr_ecc_enable);
+}

drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h

@@ -0,0 +1,29 @@
+/*
+ * GP10B specific sysfs files
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _GP10B_SYSFS_H_
+#define _GP10B_SYSFS_H_
+
+#include <linux/version.h>
+
+/*ECC Fuse*/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
+#define FUSE_OPT_ECC_EN  0x358
+#endif
+
+void gp10b_create_sysfs(struct device *dev);
+void gp10b_remove_sysfs(struct device *dev);
+
+#endif /*_GP10B_SYSFS_H_*/

drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c

@@ -0,0 +1,73 @@
+/*
+ * drivers/video/tegra/host/gp10b/gr_ctx_gp10b.c
+ *
+ * GM20B Graphics Context
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gr_ctx_gp10b.h"
+
+static int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name)
+{
+	switch (index) {
+#ifdef GP10B_NETLIST_IMAGE_FW_NAME
+	case NETLIST_FINAL:
+		sprintf(name, GP10B_NETLIST_IMAGE_FW_NAME);
+		return 0;
+#endif
+#ifdef GK20A_NETLIST_IMAGE_A
+	case NETLIST_SLOT_A:
+		sprintf(name, GK20A_NETLIST_IMAGE_A);
+		return 0;
+#endif
+#ifdef GK20A_NETLIST_IMAGE_B
+	case NETLIST_SLOT_B:
+		sprintf(name, GK20A_NETLIST_IMAGE_B);
+		return 0;
+#endif
+#ifdef GK20A_NETLIST_IMAGE_C
+	case NETLIST_SLOT_C:
+		sprintf(name, GK20A_NETLIST_IMAGE_C);
+		return 0;
+#endif
+#ifdef GK20A_NETLIST_IMAGE_D
+	case NETLIST_SLOT_D:
+		sprintf(name, GK20A_NETLIST_IMAGE_D);
+		return 0;
+#endif
+	default:
+		return -1;
+	}
+
+	return -1;
+}
+
+static bool gr_gp10b_is_firmware_defined(void)
+{
+#ifdef GP10B_NETLIST_IMAGE_FW_NAME
+	return true;
+#else
+	return false;
+#endif
+}
+
+void gp10b_init_gr_ctx(struct gpu_ops *gops) {
+	gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name;
+	gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined;
+	gops->gr_ctx.use_dma_for_fw_bootstrap = true;
+}

drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h

@@ -0,0 +1,28 @@
+/*
+ * GP10B Graphics Context
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __GR_CTX_GM10B_H__
+#define __GR_CTX_GM10B_H__
+
+#include "gk20a/gr_ctx_gk20a.h"
+
+/* production netlist, one and only one from below */
+#define GP10B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A
+
+void gp10b_init_gr_ctx(struct gpu_ops *gops);
+
+#endif /*__GR_CTX_GP10B_H__*/