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gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>

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Remove <soc/tegra/fuse.h> includes and include
<nvgpu/fuse.h> header to remove direct dependency
on platform specific header

Use specific APIs like below to read/write fuses
nvgpu_tegra_fuse_write_bypass()
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable()

Remove old code which was compiled for kernel versions
less than 4.4 since we support only k4.4 and greater
versions now

Jira NVGPU-75

Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
This commit is contained in:
Deepak Nibade
2017-05-23 18:01:43 +05:30
committed by mobile promotions
parent eb8db3e4df
commit 7d16f7e52c
8 changed files with 20 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
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@@ -30,11 +30,6 @@ struct nvgpu_firmware;
#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe)
/*Fuse defines*/
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
#define FUSE_GCPLEX_CONFIG_FUSE_0 0x2C8
#endif
bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu);
void gk20a_pmu_isr(struct gk20a *g);

4
drivers/gpu/nvgpu/gm20b/clk_gm20b.c
View File

@@ -240,8 +240,6 @@ found_match:
/* GPCPLL NA/DVFS mode methods */
#define FUSE_RESERVED_CALIB 0x204
static inline int fuse_get_gpcpll_adc_rev(u32 val)
{
return (val >> 30) & 0x3;
@@ -264,7 +262,7 @@ static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv)
u32 val;
int ret;
ret = nvgpu_tegra_fuse_read(FUSE_RESERVED_CALIB, &val);
ret = nvgpu_tegra_fuse_read_reserved_calib(&val);
if (ret)
return ret;

19
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -13,14 +13,13 @@
* more details.
*/
#include <soc/tegra/fuse.h>
#include <dt-bindings/soc/gm20b-fuse.h>
#include <nvgpu/kmem.h>
#include <nvgpu/log.h>
#include <nvgpu/enabled.h>
#include <nvgpu/debug.h>
#include <nvgpu/fuse.h>
#include "gk20a/gk20a.h"
#include "gk20a/gr_gk20a.h"
@@ -548,18 +547,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
{
tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0);
tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0);
nvgpu_tegra_fuse_write_bypass(0x1);
nvgpu_tegra_fuse_write_access_sw(0x0);
if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) {
tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0);
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0);
nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x1);
} else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) {
tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0);
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1);
nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0);
} else {
tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0);
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0);
nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0);
}
}

8
drivers/gpu/nvgpu/gm20b/gr_gm20b.h
View File

@@ -28,14 +28,6 @@ enum {
MAXWELL_CHANNEL_GPFIFO_A= 0xB06F,
};
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
#define tegra_fuse_control_write tegra_fuse_writel
#define FUSE_FUSEBYPASS_0 0x24
#define FUSE_WRITE_ACCESS_SW_0 0x30
#define FUSE_OPT_GPU_TPC0_DISABLE_0 0x30C
#define FUSE_OPT_GPU_TPC1_DISABLE_0 0x33C
#endif
#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
#define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280
#define NVB197_SET_SHADER_EXCEPTIONS 0x1528

5
drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
View File

@@ -13,10 +13,9 @@
* more details.
*/
#include <soc/tegra/fuse.h>
#include <nvgpu/timers.h>
#include <nvgpu/pmu.h>
#include <nvgpu/fuse.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
@@ -269,7 +268,7 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g)
gk20a_readl(g, fuse_opt_sec_debug_en_r()));
nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
gk20a_readl(g, fuse_opt_priv_sec_en_r()));
tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val);
nvgpu_tegra_fuse_read_gcplex_config_fuse(&val);
nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
val);
}

13
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -13,8 +13,6 @@
* more details.
*/
#include <soc/tegra/fuse.h>
#include <dt-bindings/soc/gm20b-fuse.h>
#include <dt-bindings/soc/gp10b-fuse.h>
@@ -24,6 +22,7 @@
#include <nvgpu/dma.h>
#include <nvgpu/bug.h>
#include <nvgpu/debug.h>
#include <nvgpu/fuse.h>
#include "gk20a/gk20a.h"
#include "gk20a/gr_gk20a.h"
@@ -1571,15 +1570,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g)
static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
{
tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0);
tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0);
nvgpu_tegra_fuse_write_bypass(0x1);
nvgpu_tegra_fuse_write_access_sw(0x0);
if (g->gr.gpc_tpc_mask[gpc_index] == 0x1)
tegra_fuse_control_write(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0);
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x2);
else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2)
tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1);
else
tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0);
}
static void gr_gp10b_get_access_map(struct gk20a *g,

5
drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
View File

@@ -13,10 +13,9 @@
* more details.
*/
#include <soc/tegra/fuse.h>
#include <nvgpu/pmu.h>
#include <nvgpu/log.h>
#include <nvgpu/fuse.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
@@ -383,7 +382,7 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g)
gk20a_readl(g, fuse_opt_sec_debug_en_r()));
nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
gk20a_readl(g, fuse_opt_priv_sec_en_r()));
tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val);
nvgpu_tegra_fuse_read_gcplex_config_fuse(&val);
nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
val);
}

3
drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
View File

@@ -32,9 +32,6 @@
#if defined(CONFIG_COMMON_CLK)
#include <soc/tegra/tegra-dvfs.h>
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
#include <soc/tegra/fuse.h>
#endif
#ifdef CONFIG_TEGRA_BWMGR
#include <linux/platform/tegra/emc_bwmgr.h>
#endif