gpu: nvgpu: Add api to get the physical gpc mask

1) Added a utility api to query the physical gpc mask for a
gpu instance.
2) Expose physical gpc mask during MIG case (par with legacy case).

JIRA NVGPU-5650

Change-Id: I7efb031ac6539d8859b265f42d269233a3a421bf
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510854
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2021-04-06 14:45:55 +05:30
committed by mobile promotions
parent f17d0c1c70
commit 7de19b0956
3 changed files with 30 additions and 1 deletions

View File

@@ -299,7 +299,8 @@ static int gr_config_init_mig_gpcs(struct nvgpu_gr_config *config)
return -EINVAL;
}
config->gpc_mask = nvgpu_safe_sub_u32(BIT32(config->gpc_count), 1U);
config->gpc_mask = nvgpu_grmgr_get_gr_physical_gpc_mask(
g, cur_gr_instance);
return 0;
}

View File

@@ -533,3 +533,30 @@ u32 nvgpu_grmgr_get_gr_logical_gpc_mask(struct gk20a *g, u32 gr_instance_id)
return logical_gpc_mask;
}
u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id)
{
u32 physical_gpc_mask = 0U;
u32 gpc_indx;
struct nvgpu_gpu_instance *gpu_instance;
struct nvgpu_gr_syspipe *gr_syspipe;
u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
g, gr_instance_id);
gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
gr_syspipe = &gpu_instance->gr_syspipe;
for (gpc_indx = 0U; gpc_indx < gr_syspipe->num_gpc; gpc_indx++) {
physical_gpc_mask |= BIT32(
gr_syspipe->gpcs[gpc_indx].physical_id);
nvgpu_log(g, gpu_dbg_mig,
"gpu_instance_id[%u] gr_instance_id[%u] gpc_indx[%u] "
"physical_id[%u] physical_gpc_mask[%x]",
gpu_instance_id, gr_instance_id, gpc_indx,
gr_syspipe->gpcs[gpc_indx].physical_id,
physical_gpc_mask);
}
return physical_gpc_mask;
}

View File

@@ -52,6 +52,7 @@ u32 nvgpu_grmgr_get_gpu_instance_max_veid_count(struct gk20a *g,
u32 gpu_instance_id);
u32 nvgpu_grmgr_get_gr_max_veid_count(struct gk20a *g, u32 gr_instance_id);
u32 nvgpu_grmgr_get_gr_logical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
static inline bool nvgpu_grmgr_is_mig_type_gpu_instance(
struct nvgpu_gpu_instance *gpu_instance)