gpu: nvgpu: whitelist MISRA violations due to true/false bug

Whitelist false positive violations cause by a Coverity bug that
misinterprets "true" and "false" as integers. See nvbug 2623654 for
details on the bug.

JIRA NVGPU-4031

Change-Id: Id144eac1d23be5cfaba73322c3e89c76b5664d6c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203976
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-09-23 16:13:41 -04:00
committed by Alex Waterman
parent 2a205f6aeb
commit 7f87599df9
3 changed files with 5 additions and 0 deletions

View File

@@ -45,6 +45,7 @@
} else { \
nvgpu_log(g, gpu_dbg_map, fmt, ##args); \
} \
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
} while (false)
#define nvgpu_gmmu_dbg_v(g, attrs, fmt, args...) \
@@ -54,6 +55,7 @@
} else { \
nvgpu_log(g, gpu_dbg_map_v, fmt, ##args); \
} \
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
} while (false)
static int pd_allocate(struct vm_gk20a *vm,

View File

@@ -260,6 +260,7 @@ void nvgpu_gmmu_unmap_locked(struct vm_gk20a *vm,
} else { \
nvgpu_log(g, gpu_dbg_pte, fmt, ##args); \
} \
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
} while (false)
#endif /* NVGPU_GMMU_H */

View File

@@ -23,6 +23,7 @@
#ifndef NVGPU_POSIX_COND_H
#define NVGPU_POSIX_COND_H
#include <nvgpu/static_analysis.h>
#include <nvgpu/bug.h>
#include <nvgpu/lock.h>
@@ -115,6 +116,7 @@ do { \
ret = nvgpu_cond_timedwait(cond, \
&cond_wait_timeout_timeout); \
} \
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
} while (false)
#endif /* NVGPU_POSIX_COND_H */