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gpu: nvgpu: whitelist MISRA violations due to true/false bug
Whitelist false positive violations cause by a Coverity bug that misinterprets "true" and "false" as integers. See nvbug 2623654 for details on the bug. JIRA NVGPU-4031 Change-Id: Id144eac1d23be5cfaba73322c3e89c76b5664d6c Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2203976 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Alex Waterman
parent
2a205f6aeb
commit
7f87599df9
@@ -45,6 +45,7 @@
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} else { \
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nvgpu_log(g, gpu_dbg_map, fmt, ##args); \
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} \
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NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
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} while (false)
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#define nvgpu_gmmu_dbg_v(g, attrs, fmt, args...) \
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@@ -54,6 +55,7 @@
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} else { \
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nvgpu_log(g, gpu_dbg_map_v, fmt, ##args); \
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} \
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NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
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} while (false)
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static int pd_allocate(struct vm_gk20a *vm,
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@@ -260,6 +260,7 @@ void nvgpu_gmmu_unmap_locked(struct vm_gk20a *vm,
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} else { \
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nvgpu_log(g, gpu_dbg_pte, fmt, ##args); \
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} \
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NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
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} while (false)
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#endif /* NVGPU_GMMU_H */
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@@ -23,6 +23,7 @@
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#ifndef NVGPU_POSIX_COND_H
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#define NVGPU_POSIX_COND_H
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/lock.h>
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@@ -115,6 +116,7 @@ do { \
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ret = nvgpu_cond_timedwait(cond, \
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&cond_wait_timeout_timeout); \
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} \
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NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
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} while (false)
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#endif /* NVGPU_POSIX_COND_H */
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