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gpu: nvgpu: Set GPC PLL id in platform probe
Set GPC PLL id in Tegra platform probe, to match Tegra SoC. Bug 1851797 Bug 1867980 Change-Id: Ie6d2625a0009bcb96511aeda8c5af4734cf04929 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1461698 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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@@ -24,6 +24,9 @@
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enum {
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/* only one PLL for gk20a */
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GK20A_GPC_PLL = 0,
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/* 2 PLL revisions for gm20b */
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GM20B_GPC_PLL_B1,
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GM20B_GPC_PLL_C1,
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};
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enum gpc_pll_mode {
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@@ -943,15 +943,20 @@ static int gk20a_tegra_probe(struct device *dev)
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platform->can_railgate = false;
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}
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/* WAR for bug 1547668: Disable railgating and scaling irrespective of
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* platform data if the rework has not been made. */
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platform->g->clk.gpc_pll.id = GK20A_GPC_PLL;
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if (tegra_get_chip_id() == TEGRA210) {
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/* WAR for bug 1547668: Disable railgating and scaling
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irrespective of platform data if the rework was not made. */
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np = of_find_node_by_path("/gpu-dvfs-rework");
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if (!(np && of_device_is_available(np))) {
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platform->devfreq_governor = "";
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dev_warn(dev, "board does not support scaling");
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}
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platform->g->clk.gpc_pll.id = GM20B_GPC_PLL_B1;
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
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if (tegra_chip_get_revision() > TEGRA210_REVISION_A04p)
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platform->g->clk.gpc_pll.id = GM20B_GPC_PLL_C1;
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#endif
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}
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if (tegra_get_chip_id() == TEGRA132)
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