nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 11:04:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu:nvgpu: Support to bootstrap ctxsw in MIG mode

Browse Source 
-Update PMU_RPC_STRUCT_ACR_BOOTSTRAP_FALCON to
 accpet the FECS/GPCCS instance bootstrap request.
-Update the ACR ucode interface to take MIG mode
 param to config FECS/GPCCS SCTL PLM for LSPMU access.

JIRA NVGPU-6562

Change-Id: I460ef4e965009b3a77aeb4350f2191235f52c6f7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2587033
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2021-09-08 05:02:09 +00:00
committed by mobile promotions
parent af24bff07d
commit 82526439dc
5 changed files with 143 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c
View File

@@ -160,7 +160,14 @@ static int ga10b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
acr_sysmem_desc->gpu_mode &= (~EMULATE_MODE_MASK);
acr_sysmem_desc->gpu_mode |= g->emulate_mode;
}
}
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
acr_sysmem_desc->gpu_mode |= MIG_MODE;
} else {
acr_sysmem_desc->gpu_mode &= ~MIG_MODE;
}
}
load:
/*
* Push the acr descriptor data to sysmem.
@@ -233,8 +240,11 @@ static u32 ga10b_acr_lsf_fecs(struct gk20a *g,
* not supported.
*/
lsf->is_lazy_bootstrap = g->support_ls_pmu ? true : false;
lsf->is_priv_load = false;
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
lsf->is_priv_load = true;
} else {
lsf->is_priv_load = false;
}
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details;
lsf->get_cmd_line_args_offset = NULL;
@@ -256,7 +266,6 @@ static u32 ga10b_acr_lsf_gpccs(struct gk20a *g,
* not supported.
*/
lsf->is_lazy_bootstrap = g->support_ls_pmu ? true : false;
lsf->is_priv_load = true;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details;
lsf->get_cmd_line_args_offset = NULL;

3
drivers/gpu/nvgpu/common/acr/nvgpu_acr_interface.h
View File

@@ -743,6 +743,9 @@ struct flcn_acr_desc {
u32 dummy[DUMMY_SPACE_SIZE];
};
/* MIG mode selection*/
#define MIG_MODE BIT(8U)
struct flcn2_acr_desc {
/**
* WPR Region ID holding the WPR header and its details

21
drivers/gpu/nvgpu/common/pmu/lsfm/lsfm.c
View File

@@ -69,14 +69,25 @@ int nvgpu_pmu_lsfm_int_wpr_region(struct gk20a *g,
int nvgpu_pmu_lsfm_bootstrap_ls_falcon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_lsfm *lsfm, u32 falcon_id_mask)
{
int status = 0;
if (is_lsfm_supported(g, pmu, lsfm)) {
if (lsfm->bootstrap_ls_falcon != NULL) {
return lsfm->bootstrap_ls_falcon(g, pmu, lsfm,
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
if (lsfm->bootstrap_ls_falcon != NULL) {
status = lsfm->bootstrap_ls_falcon(g, pmu, lsfm,
falcon_id_mask);
}
} else {
status = lsfm->bootstrap_ls_falcon(g, pmu, lsfm, FALCON_ID_FECS);
if (status != 0) {
return status;
}
status = lsfm->bootstrap_ls_falcon(g, pmu, lsfm, FALCON_ID_GPCCS);
}
}
return 0;
return status;
}
int nvgpu_pmu_lsfm_ls_pmu_cmdline_args_copy(struct gk20a *g,
@@ -112,6 +123,10 @@ void nvgpu_pmu_lsfm_rpc_handler(struct gk20a *g,
"reply NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS");
pmu->lsfm->loaded_falcon_id = 1U;
break;
case NV_PMU_RPC_ID_ACR_BOOTSTRAP_FALCON:
nvgpu_pmu_dbg(g, "reply NV_PMU_RPC_ID_ACR_BOOTSTRAP_FALCON");
pmu->lsfm->loaded_falcon_id = 1U;
break;
default:
nvgpu_pmu_dbg(g, "unsupported ACR function");
break;

84
drivers/gpu/nvgpu/common/pmu/lsfm/lsfm_sw_gv100.c
View File

@@ -28,9 +28,14 @@
#include <nvgpu/pmu/cmd.h>
#include <nvgpu/pmu/lsfm.h>
#include <nvgpu/pmu/fw.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr_utils.h>
#include <nvgpu/gr/gr_instances.h>
#include "lsfm_sw_gv100.h"
#define LSF_INDEX_MASK_DEFAULT 0x0U
static int gv100_pmu_lsfm_init_acr_wpr_region(struct gk20a *g,
struct nvgpu_pmu *pmu)
{
@@ -104,6 +109,79 @@ exit:
return status;
}
static u32 fetch_gpc_falcon_idx_mask(struct gk20a *g)
{
u32 gpc_falcon_idx_mask = 0U;
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
gpc_falcon_idx_mask = nvgpu_grmgr_get_gr_logical_gpc_mask(g,
nvgpu_gr_get_cur_instance_id(g));
} else {
u32 gpc_fs_mask;
struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
gpc_fs_mask = nvgpu_gr_config_get_gpc_mask(gr_config);
gpc_falcon_idx_mask =
nvgpu_safe_sub_u32(
(1U << U32(hweight32(gpc_fs_mask))), 1U);
}
return gpc_falcon_idx_mask;
}
static int gv100_pmu_lsfm_bootstrap_ls_falcon_eng(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_lsfm *lsfm, u32 falcon_id)
{
struct nv_pmu_rpc_struct_acr_bootstrap_falcon rpc;
u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
int status = 0;
lsfm->loaded_falcon_id = 0U;
/* check whether pmu is ready to bootstrap lsf if not wait for it */
if (!lsfm->is_wpr_init_done) {
pmu_wait_message_cond(g->pmu,
nvgpu_get_poll_timeout(g),
&lsfm->is_wpr_init_done, 1U);
/* check again if it still not ready indicate an error */
if (!lsfm->is_wpr_init_done) {
nvgpu_err(g, "PMU not ready to load LSF");
status = -ETIMEDOUT;
goto exit;
}
}
(void) memset(&rpc, 0,
sizeof(struct nv_pmu_rpc_struct_acr_bootstrap_falcon));
rpc.falcon_id = falcon_id;
rpc.flags = flags;
rpc.engine_instance =
nvgpu_grmgr_get_gr_syspipe_id(g,
nvgpu_gr_get_cur_instance_id(g));
rpc.engine_index_mask = LSF_INDEX_MASK_DEFAULT;
if (falcon_id == FALCON_ID_GPCCS) {
rpc.engine_index_mask = fetch_gpc_falcon_idx_mask(g);
}
PMU_RPC_EXECUTE(status, pmu, ACR, BOOTSTRAP_FALCON, &rpc, 0);
if (status != 0) {
nvgpu_err(g, "Failed to execute RPC, status=0x%x", status);
goto exit;
}
pmu_wait_message_cond(g->pmu, nvgpu_get_poll_timeout(g),
&lsfm->loaded_falcon_id, 1U);
if (lsfm->loaded_falcon_id != 1U) {
status = -ETIMEDOUT;
}
exit:
return status;
}
int gv100_update_lspmu_cmdline_args_copy(struct gk20a *g,
struct nvgpu_pmu *pmu)
{
@@ -145,6 +223,10 @@ void nvgpu_gv100_lsfm_sw_init(struct gk20a *g, struct nvgpu_pmu_lsfm *lsfm)
lsfm->loaded_falcon_id = 0U;
lsfm->init_wpr_region = gv100_pmu_lsfm_init_acr_wpr_region;
lsfm->bootstrap_ls_falcon = gv100_pmu_lsfm_bootstrap_ls_falcon;
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
lsfm->bootstrap_ls_falcon = gv100_pmu_lsfm_bootstrap_ls_falcon;
} else {
lsfm->bootstrap_ls_falcon = gv100_pmu_lsfm_bootstrap_ls_falcon_eng;
}
lsfm->ls_pmu_cmdline_args_copy = gv100_update_lspmu_cmdline_args_copy;
}

27
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/acr.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -159,4 +159,29 @@ struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons {
u32 scratch[1];
};
/*
* structure that holds data used to
* execute BOOTSTRAP_FALCON RPC.
*/
struct nv_pmu_rpc_struct_acr_bootstrap_falcon {
/*[IN/OUT] Must be first field in RPC structure */
struct nv_pmu_rpc_header hdr;
/* [IN] Falcon ID */
u32 falcon_id;
/* [IN] Engine Instance to be bootstrapped by ACR */
u32 engine_instance;
/* [IN] Mask of indexes of same engine to be multi bootstrapped by ACR */
u32 engine_index_mask;
/*
* [IN] Boostrapping flags
*/
u32 flags;
u32 scratch[1];
};
#endif /* NVGPU_PMUIF_ACR_H */