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gpu: nvgpu: initialize ctx state for each GR instance

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Execute nvgpu_gr_init_ctx_state() for each GR instance. Move it under
gr_init_ctxsw_falcon_support() which is already executed for each
instance.

Update the API to accept struct nvgpu_gr pointer for convenience. API
does not need to know about other instances.

For reset path, continue using g->gr instead of specific instance.
This will be revisited when entire reset path is refactored.

Jira NVGPU-5648

Change-Id: I8879bf3b44bb01f6b8053f1aecbd550f49837520
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2409535
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2020-09-07 14:52:41 +05:30
committed by Alex Waterman
parent 8d2cb311cb
commit 83691e088f
1 changed files with 18 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/gpu/nvgpu/common/gr/gr.c
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@@ -402,12 +402,12 @@ static int gr_init_config(struct gk20a *g)
return 0; return 0;
} }
static int nvgpu_gr_init_ctx_state(struct gk20a *g) static int nvgpu_gr_init_ctx_state(struct gk20a *g, struct nvgpu_gr *gr)
{ {
int err = 0; int err = 0;
/* Initialize ctx state during boot and recovery */ /* Initialize ctx state during boot and recovery */
err = nvgpu_gr_falcon_init_ctx_state(g, g->gr->falcon); err = nvgpu_gr_falcon_init_ctx_state(g, gr->falcon);
if (err != 0) { if (err != 0) {
nvgpu_err(g, "gr ctx_state init failed"); nvgpu_err(g, "gr ctx_state init failed");
} }
@@ -716,9 +716,12 @@ int nvgpu_gr_reset(struct gk20a *g)
nvgpu_mutex_release(fecs_mutex); nvgpu_mutex_release(fecs_mutex);
/* this appears query for sw states but fecs actually init /*
ramchain, etc so this is hw init */ * This appears query for sw states but fecs actually inits
err = nvgpu_gr_init_ctx_state(g); * ramchain, etc so this is hw init. Hence should be executed
* for every GR engine HW initialization.
*/
err = nvgpu_gr_init_ctx_state(g, g->gr);
if (err != 0) { if (err != 0) {
return err; return err;
} }
@@ -771,6 +774,16 @@ static int gr_init_ctxsw_falcon_support(struct gk20a *g)
return err; return err;
} }
/*
* This appears query for sw states but fecs actually inits
* ramchain, etc so this is hw init. Hence should be executed
* for every GR engine HW initialization.
*/
err = nvgpu_gr_init_ctx_state(g, gr);
if (err != 0) {
return err;
}
return 0; return 0;
} }
@@ -808,13 +821,6 @@ int nvgpu_gr_init_support(struct gk20a *g)
return err; return err;
} }
/* this appears query for sw states but fecs actually init
ramchain, etc so this is hw init */
err = nvgpu_gr_init_ctx_state(g);
if (err != 0) {
return err;
}
#ifdef CONFIG_NVGPU_POWER_PG #ifdef CONFIG_NVGPU_POWER_PG
if (g->can_elpg) { if (g->can_elpg) {
err = nvgpu_gr_falcon_bind_fecs_elpg(g); err = nvgpu_gr_falcon_bind_fecs_elpg(g);