gpu: nvgpu: mclk switching sequences for PG419

VBIOS memory settings have been updated for PG419, significantly
modifying MCLK switching sequences. This change adds support for
PG419 tables, while remaining backward compatible with PG418.

Bug 1921082
JIRA EVLR-1269

Change-Id: Ia8a1f8b3f482e348a46f0acb540af23287d9c11e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1484110
(cherry picked from commit c2444ae89caf97da2702e8486cc8fb162b4f50b1)
Reviewed-on: http://git-master/r/1485300
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/clk/clk_arb.c

@@ -1989,7 +1989,7 @@ static int nvgpu_clk_arb_change_vf_point(struct gk20a *g, u16 gpc2clk_target,
 
 	/* descending */
 	if (voltuv < arb->voltuv_actual) {
-		status = g->clk_pmu.clk_mclk.change(g, mclk_target);
+		status = g->ops.pmu.mclk_change(g, mclk_target);
 		if (status < 0)
 			return status;
 
@@ -2009,7 +2009,7 @@ static int nvgpu_clk_arb_change_vf_point(struct gk20a *g, u16 gpc2clk_target,
 		if (status < 0)
 			return status;
 
-		status = g->clk_pmu.clk_mclk.change(g, mclk_target);
+		status = g->ops.pmu.mclk_change(g, mclk_target);
 		if (status < 0)
 			return status;
 	}

drivers/gpu/nvgpu/clk/clk_mclk.h

@@ -16,6 +16,14 @@
 
 #include <nvgpu/lock.h>
 
+#define GP106_MCLK_LOW_SPEED	0
+#define GP106_MCLK_MID_SPEED	1
+#define GP106_MCLK_HIGH_SPEED	2
+#define GP106_MCLK_NUM_SPEED	3
+
+#define GP106_MEM_CONFIG_GDDR5_PG418	0
+#define GP106_MEM_CONFIG_GDDR5_PG419	1
+
 enum gk20a_mclk_speed {
 	gk20a_mclk_low_speed,
 	gk20a_mclk_mid_speed,
@@ -23,7 +31,7 @@ enum gk20a_mclk_speed {
 };
 
 struct clk_mclk_state {
-	enum gk20a_mclk_speed speed;
+	u32 speed;
 	struct nvgpu_mutex mclk_lock;
 	struct nvgpu_mutex data_lock;
 
@@ -33,9 +41,6 @@ struct clk_mclk_state {
 	void *vreg_buf;
 	bool init;
 
-	/* function pointers */
-	int (*change)(struct gk20a *g, u16 val);
-
 #ifdef CONFIG_DEBUG_FS
 	s64 switch_max;
 	s64 switch_min;

drivers/gpu/nvgpu/common/linux/pci.c

@@ -25,6 +25,7 @@
 #include "gk20a/gk20a.h"
 #include "gk20a/platform_gk20a.h"
 #include "clk/clk.h"
+#include "clk/clk_mclk.h"
 #include "module.h"
 #include "intr.h"
 
@@ -92,6 +93,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
 	.ina3221_dcb_index = 0,
 	.ina3221_i2c_address = 0x84,
 	.ina3221_i2c_port = 0x2,
+	.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
 	},
 	{ /* DEVICE=0x1c36 */
 	/* ptimer src frequency in hz */
@@ -127,6 +129,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
 	.ina3221_dcb_index = 0,
 	.ina3221_i2c_address = 0x84,
 	.ina3221_i2c_port = 0x2,
+	.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
 	},
 	{ /* DEVICE=0x1c37 */
 	/* ptimer src frequency in hz */
@@ -162,6 +165,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
 	.ina3221_dcb_index = 0,
 	.ina3221_i2c_address = 0x84,
 	.ina3221_i2c_port = 0x2,
+	.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
 	},
 	{ /* DEVICE=0x1c75 */
 	/* ptimer src frequency in hz */
@@ -197,6 +201,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
 	.ina3221_dcb_index = 1,
 	.ina3221_i2c_address = 0x80,
 	.ina3221_i2c_port = 0x1,
+	.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG419,
 	}
 };
 
@@ -392,6 +397,8 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
 		g->msi_enabled = true;
 #endif
 
+	g->mem_config_idx = platform->mem_config_idx;
+
 	g->irq_stall = pdev->irq;
 	g->irq_nonstall = pdev->irq;
 	if (g->irq_stall < 0)

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -775,6 +775,7 @@ struct gpu_ops {
 			void *lsfm,	u32 *p_bl_gen_desc_size, u32 falconid);
 		int (*mclk_init)(struct gk20a *g);
 		void (*mclk_deinit)(struct gk20a *g);
+		int (*mclk_change)(struct gk20a *g, u16 val);
 		u32  lspmuwprinitdone;
 		u32  lsfloadedfalconid;
 		bool fecsbootstrapdone;
@@ -1286,12 +1287,14 @@ struct gk20a {
 	 * from monitoring power, current and voltage */
 	bool power_sensor_missing;
 
+	/* memory training sequence and mclk switch scripts */
+	u32 mem_config_idx;
+
 #if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
 	phys_addr_t	syncpt_unit_base;
 	size_t		syncpt_unit_size;
 	u32		syncpt_size;
 #endif
-
 };
 
 static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)

drivers/gpu/nvgpu/gk20a/platform_gk20a.h

@@ -235,6 +235,9 @@ struct gk20a_platform {
 	u32 ina3221_dcb_index;
 	u32 ina3221_i2c_address;
 	u32 ina3221_i2c_port;
+
+	/* memory training pattern and mclk switch sequences */
+	u8 mem_config_idx;
 };
 
 static inline struct gk20a_platform *gk20a_get_platform(