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gpu: nvgpu: mclk switching sequences for PG419
VBIOS memory settings have been updated for PG419, significantly modifying MCLK switching sequences. This change adds support for PG419 tables, while remaining backward compatible with PG418. Bug 1921082 JIRA EVLR-1269 Change-Id: Ia8a1f8b3f482e348a46f0acb540af23287d9c11e Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1484110 (cherry picked from commit c2444ae89caf97da2702e8486cc8fb162b4f50b1) Reviewed-on: http://git-master/r/1485300 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -25,6 +25,7 @@
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#include "gk20a/gk20a.h"
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#include "gk20a/platform_gk20a.h"
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#include "clk/clk.h"
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#include "clk/clk_mclk.h"
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#include "module.h"
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#include "intr.h"
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@@ -92,6 +93,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.ina3221_dcb_index = 0,
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.ina3221_i2c_address = 0x84,
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.ina3221_i2c_port = 0x2,
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.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
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},
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{ /* DEVICE=0x1c36 */
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/* ptimer src frequency in hz */
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@@ -127,6 +129,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.ina3221_dcb_index = 0,
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.ina3221_i2c_address = 0x84,
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.ina3221_i2c_port = 0x2,
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.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
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},
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{ /* DEVICE=0x1c37 */
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/* ptimer src frequency in hz */
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@@ -162,6 +165,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.ina3221_dcb_index = 0,
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.ina3221_i2c_address = 0x84,
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.ina3221_i2c_port = 0x2,
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.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
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},
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{ /* DEVICE=0x1c75 */
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/* ptimer src frequency in hz */
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@@ -197,6 +201,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.ina3221_dcb_index = 1,
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.ina3221_i2c_address = 0x80,
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.ina3221_i2c_port = 0x1,
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.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG419,
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}
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};
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@@ -392,6 +397,8 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
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g->msi_enabled = true;
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#endif
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g->mem_config_idx = platform->mem_config_idx;
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g->irq_stall = pdev->irq;
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g->irq_nonstall = pdev->irq;
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if (g->irq_stall < 0)
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