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gpu: nvgpu: update SEC2 falcon base addr init

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SEC2 falcon base address was being set without invoking hal api. Remove
FALCON_SEC_BASE. This patch defines gpu_ops.sec2.falcon_base_addr hal api
to get this base address.
Also, don't initialize the base for non-supported falcons.

JIRA NVGPU-1587

Change-Id: Iad19a9987416076cf9090d30a48ff83369cf73c2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969429
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2018-12-10 12:05:50 +05:30
committed by mobile promotions
parent e6668a163f
commit 84b493e644
12 changed files with 25 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
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@@ -727,11 +727,6 @@ int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true;
break;
case FALCON_ID_SEC2:
flcn->flcn_base = FALCON_SEC_BASE;
flcn->is_falcon_supported = false;
flcn->is_interrupt_enabled = false;
break;
case FALCON_ID_FECS:
flcn->flcn_base = FALCON_FECS_BASE;
flcn->is_falcon_supported = true;

2
drivers/gpu/nvgpu/common/falcon/falcon_gp106.c
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@@ -66,7 +66,7 @@ int gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
flcn->is_interrupt_enabled = true;
break;
case FALCON_ID_SEC2:
flcn->flcn_base = FALCON_SEC_BASE;
flcn->flcn_base = g->ops.sec2.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;

2
drivers/gpu/nvgpu/common/falcon/falcon_tu104.c
View File

@@ -63,7 +63,7 @@ int tu104_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
switch (flcn->flcn_id) {
case FALCON_ID_SEC2:
flcn->flcn_base = psec_falcon_irqsset_r();
flcn->flcn_base = g->ops.sec2.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true;
break;

4
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -917,6 +917,9 @@ static const struct gpu_ops gp106_ops = {
.acr = {
.acr_sw_init = nvgpu_gp106_acr_sw_init,
},
.sec2 = {
.falcon_base_addr = gp106_sec2_falcon_base_addr,
},
.get_litter_value = gp106_get_litter_value,
.chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
};
@@ -976,6 +979,7 @@ int gp106_init_hal(struct gk20a *g)
gops->priv_ring = gp106_ops.priv_ring;
gops->fuse = gp106_ops.fuse;
gops->acr = gp106_ops.acr;
gops->sec2 = gp106_ops.sec2;
/* Lone functions */
gops->get_litter_value = gp106_ops.get_litter_value;

5
drivers/gpu/nvgpu/gp106/sec2_gp106.c
View File

@@ -115,3 +115,8 @@ int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
return sec2_flcn_bl_bootstrap(g, bl_info);
}
u32 gp106_sec2_falcon_base_addr(void)
{
return psec_falcon_irqsset_r();
}

2
drivers/gpu/nvgpu/gp106/sec2_gp106.h
View File

@@ -29,4 +29,6 @@ int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
struct hs_acr *acr_desc,
struct nvgpu_falcon_bl_info *bl_info);
u32 gp106_sec2_falcon_base_addr(void);
#endif /* NVGPU_SEC2_GP106_H */

4
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -1083,6 +1083,9 @@ static const struct gpu_ops gv100_ops = {
.acr = {
.acr_sw_init = nvgpu_gp106_acr_sw_init,
},
.sec2 = {
.falcon_base_addr = gp106_sec2_falcon_base_addr,
},
.chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
.get_litter_value = gv100_get_litter_value,
};
@@ -1126,6 +1129,7 @@ int gv100_init_hal(struct gk20a *g)
gops->nvlink = gv100_ops.nvlink;
gops->top = gv100_ops.top;
gops->acr = gv100_ops.acr;
gops->sec2 = gv100_ops.sec2;
/* clocks */
gops->clk.init_clk_support = gv100_ops.clk.init_clk_support;

1
drivers/gpu/nvgpu/include/nvgpu/falcon.h
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@@ -42,7 +42,6 @@
/*
* Falcon Base address Defines
*/
#define FALCON_SEC_BASE 0x00087000U
#define FALCON_FECS_BASE 0x00409000U
#define FALCON_GPCCS_BASE 0x0041a000U

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1480,6 +1480,7 @@ struct gpu_ops {
void (*isr)(struct gk20a *g);
void (*msgq_tail)(struct gk20a *g, struct nvgpu_sec2 *sec2,
u32 *tail, bool set);
u32 (*falcon_base_addr)(void);
} sec2;
void (*semaphore_wakeup)(struct gk20a *g, bool post_events);
};

1
drivers/gpu/nvgpu/tu104/hal_tu104.c
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@@ -1108,6 +1108,7 @@ static const struct gpu_ops tu104_ops = {
.is_interrupted = tu104_sec2_is_interrupted,
.isr = tu104_sec2_isr,
.msgq_tail = tu104_sec2_msgq_tail,
.falcon_base_addr = tu104_sec2_falcon_base_addr,
},
.chip_init_gpu_characteristics = tu104_init_gpu_characteristics,
.get_litter_value = tu104_get_litter_value,

5
drivers/gpu/nvgpu/tu104/sec2_tu104.c
View File

@@ -442,3 +442,8 @@ void tu104_start_sec2_secure(struct gk20a *g)
gk20a_writel(g, psec_falcon_cpuctl_alias_r(),
psec_falcon_cpuctl_alias_startcpu_f(1U));
}
u32 tu104_sec2_falcon_base_addr(void)
{
return psec_falcon_irqsset_r();
}

1
drivers/gpu/nvgpu/tu104/sec2_tu104.h
View File

@@ -45,5 +45,6 @@ void tu104_sec2_isr(struct gk20a *g);
bool tu104_sec2_is_interrupted(struct nvgpu_sec2 *sec2);
void tu104_sec2_enable_irq(struct nvgpu_sec2 *sec2, bool enable);
void tu104_start_sec2_secure(struct gk20a *g);
u32 tu104_sec2_falcon_base_addr(void);
#endif /* NVGPU_SEC2_TU104_H */