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gpu: nvgpu: move exec_reg_ops() to regops HAL

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We right now define HAL exec_reg_ops() under gops.dbg_session_ops operations
But we have separate gops.regops operations for all the regops and this would
be logically correct place for exec_reg_ops()

Move exec_reg_ops() from gops.dbg_session_ops to gops.regops
Also rename it to exec_regops()

Jira NVGPU-620

Change-Id: If4f70639ffbc892c605f7540a83bce12ed821b52
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794999
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-08-08 14:53:08 +05:30
committed by mobile promotions
parent 542e6a0ab4
commit 84c0ab81ab
9 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -1100,6 +1100,9 @@ struct gpu_ops {
int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg);
} perf;
struct {
int (*exec_regops)(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops);
const struct regop_offset_range* (
*get_global_whitelist_ranges)(void);
int (*get_global_whitelist_ranges_count)(void);
@@ -1147,9 +1150,6 @@ struct gpu_ops {
struct gk20a_debug_output *o);
} debug;
struct {
int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops);
int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s,
bool disable_powergate);
bool (*check_and_set_global_reservation)(

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -555,6 +555,7 @@ static const struct gpu_ops gm20b_ops = {
.get_pll_debug_data = gm20b_clk_get_pll_debug_data,
},
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
gm20b_get_global_whitelist_ranges,
.get_global_whitelist_ranges_count =
@@ -603,7 +604,6 @@ static const struct gpu_ops gm20b_ops = {
.post_events = gk20a_dbg_gpu_post_events,
},
.dbg_session_ops = {
.exec_reg_ops = exec_regops_gk20a,
.dbg_set_powergate = dbg_set_powergate,
.check_and_set_global_reservation =
nvgpu_check_and_set_global_reservation,

2
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -672,6 +672,7 @@ static const struct gpu_ops gp106_ops = {
.get_current_pstate = nvgpu_clk_arb_get_current_pstate,
},
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
gp106_get_global_whitelist_ranges,
.get_global_whitelist_ranges_count =
@@ -720,7 +721,6 @@ static const struct gpu_ops gp106_ops = {
.post_events = gk20a_dbg_gpu_post_events,
},
.dbg_session_ops = {
.exec_reg_ops = exec_regops_gk20a,
.dbg_set_powergate = dbg_set_powergate,
.check_and_set_global_reservation =
nvgpu_check_and_set_global_reservation,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -600,6 +600,7 @@ static const struct gpu_ops gp10b_ops = {
.get_irqdest = gk20a_pmu_get_irqdest,
},
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
gp10b_get_global_whitelist_ranges,
.get_global_whitelist_ranges_count =
@@ -648,7 +649,6 @@ static const struct gpu_ops gp10b_ops = {
.post_events = gk20a_dbg_gpu_post_events,
},
.dbg_session_ops = {
.exec_reg_ops = exec_regops_gk20a,
.dbg_set_powergate = dbg_set_powergate,
.check_and_set_global_reservation =
nvgpu_check_and_set_global_reservation,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -763,6 +763,7 @@ static const struct gpu_ops gv100_ops = {
.get_current_pstate = nvgpu_clk_arb_get_current_pstate,
},
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
gv100_get_global_whitelist_ranges,
.get_global_whitelist_ranges_count =
@@ -815,7 +816,6 @@ static const struct gpu_ops gv100_ops = {
.post_events = gk20a_dbg_gpu_post_events,
},
.dbg_session_ops = {
.exec_reg_ops = exec_regops_gk20a,
.dbg_set_powergate = dbg_set_powergate,
.check_and_set_global_reservation =
nvgpu_check_and_set_global_reservation,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -696,6 +696,7 @@ static const struct gpu_ops gv11b_ops = {
.handle_ext_irq = gv11b_pmu_handle_ext_irq,
},
.regops = {
.exec_regops = exec_regops_gk20a,
.get_global_whitelist_ranges =
gv11b_get_global_whitelist_ranges,
.get_global_whitelist_ranges_count =
@@ -747,7 +748,6 @@ static const struct gpu_ops gv11b_ops = {
.post_events = gk20a_dbg_gpu_post_events,
},
.dbg_session_ops = {
.exec_reg_ops = exec_regops_gk20a,
.dbg_set_powergate = dbg_set_powergate,
.check_and_set_global_reservation =
nvgpu_check_and_set_global_reservation,

2
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
View File

@@ -935,7 +935,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
if (err)
break;
err = g->ops.dbg_session_ops.exec_reg_ops(
err = g->ops.regops.exec_regops(
dbg_s, g->dbg_regops_tmp_buf, num_ops);
if (err) {

2
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -466,6 +466,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
},
.regops = {
.exec_regops = vgpu_exec_regops,
.get_global_whitelist_ranges =
gp10b_get_global_whitelist_ranges,
.get_global_whitelist_ranges_count =
@@ -514,7 +515,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.post_events = gk20a_dbg_gpu_post_events,
},
.dbg_session_ops = {
.exec_reg_ops = vgpu_exec_regops,
.dbg_set_powergate = vgpu_dbg_set_powergate,
.check_and_set_global_reservation =
vgpu_check_and_set_global_reservation,

2
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -535,6 +535,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.is_pmu_supported = gv11b_is_pmu_supported,
},
.regops = {
.exec_regops = vgpu_exec_regops,
.get_global_whitelist_ranges =
gv11b_get_global_whitelist_ranges,
.get_global_whitelist_ranges_count =
@@ -584,7 +585,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.post_events = gk20a_dbg_gpu_post_events,
},
.dbg_session_ops = {
.exec_reg_ops = vgpu_exec_regops,
.dbg_set_powergate = vgpu_dbg_set_powergate,
.check_and_set_global_reservation =
vgpu_check_and_set_global_reservation,