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gpu: nvgpu: vf inject changes

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- Added vf change inject support for gv10x
- Updated clk_pmu_vf_inject() to fill required data
for pascal or volta vf change inject support
- Added new ctrl clk interface for gv10x clk domain list
- Added pmu interface for gv10x clk domain list &
vf change inject request
- Modified clk cmd, msg & RPC id's to match
with chips_a_23609936 branch

Bug 200399373

Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700746
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vaikundanathan S
2018-04-23 16:52:43 +05:30
committed by mobile promotions
parent a51eb9da02
commit 85f9729af4
7 changed files with 115 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

89
drivers/gpu/nvgpu/clk/clk.c
View File

@@ -219,31 +219,13 @@ done:
return status;
}
static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
struct nv_pmu_clk_rpc *rpccall,
struct set_fll_clk *setfllclk)
{
struct pmu_cmd cmd;
struct pmu_payload payload;
u32 status;
u32 seqdesc;
struct nv_pmu_clk_rpc rpccall;
struct clkrpc_pmucmdhandler_params handler;
struct nv_pmu_clk_vf_change_inject *vfchange;
memset(&payload, 0, sizeof(struct pmu_payload));
memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) ||
(setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0))
return -EINVAL;
if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) ||
(setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) ||
(setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR))
return -EINVAL;
rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT;
vfchange = &rpccall.params.clk_vf_change_inject;
vfchange = &rpccall->params.clk_vf_change_inject;
vfchange->flags = 0;
vfchange->clk_list.num_domains = 3;
vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPC2CLK;
@@ -276,6 +258,69 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv =
setfllclk->voltuv;
return 0;
}
u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
struct nv_pmu_clk_rpc *rpccall,
struct set_fll_clk *setfllclk)
{
struct nv_pmu_clk_vf_change_inject_v1 *vfchange;
vfchange = &rpccall->params.clk_vf_change_inject_v1;
vfchange->flags = 0;
vfchange->clk_list.num_domains = 4;
vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPCCLK;
vfchange->clk_list.clk_domains[0].clk_freq_khz =
setfllclk->gpc2clkmhz * 1000;
vfchange->clk_list.clk_domains[1].clk_domain = CTRL_CLK_DOMAIN_XBARCLK;
vfchange->clk_list.clk_domains[1].clk_freq_khz =
setfllclk->xbar2clkmhz * 1000;
vfchange->clk_list.clk_domains[2].clk_domain = CTRL_CLK_DOMAIN_SYSCLK;
vfchange->clk_list.clk_domains[2].clk_freq_khz =
setfllclk->sys2clkmhz * 1000;
vfchange->clk_list.clk_domains[3].clk_domain = CTRL_CLK_DOMAIN_NVDCLK;
vfchange->clk_list.clk_domains[3].clk_freq_khz = 855 * 1000;
vfchange->volt_list.num_rails = 1;
vfchange->volt_list.rails[0].rail_idx = 0;
vfchange->volt_list.rails[0].voltage_uv = setfllclk->voltuv;
vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv =
setfllclk->voltuv;
return 0;
}
static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
{
struct pmu_cmd cmd;
struct pmu_payload payload;
u32 status;
u32 seqdesc;
struct nv_pmu_clk_rpc rpccall;
struct clkrpc_pmucmdhandler_params handler;
memset(&payload, 0, sizeof(struct pmu_payload));
memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) ||
(setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0))
return -EINVAL;
if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) ||
(setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) ||
(setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR))
return -EINVAL;
rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT;
g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill(g,
&rpccall, setfllclk);
cmd.hdr.unit_id = PMU_UNIT_CLK;
cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) +
(u32)sizeof(struct pmu_hdr);

6
drivers/gpu/nvgpu/clk/clk.h
View File

@@ -127,4 +127,10 @@ u32 clk_domain_get_f_points(
int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx);
u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
struct nv_pmu_clk_rpc *rpccall,
struct set_fll_clk *setfllclk);
u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
struct nv_pmu_clk_rpc *rpccall,
struct set_fll_clk *setfllclk);
#endif

4
drivers/gpu/nvgpu/common/pmu/pmu_fw.c
View File

@@ -1309,6 +1309,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
nvgpu_clk_get_vbios_clk_domain_gv10x;
g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data =
clk_avfs_get_vin_cal_fuse_v20;
g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill =
nvgpu_clk_vf_change_inject_data_fill_gv10x;
} else {
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
get_pmu_init_msg_pmu_queue_params_v4;
@@ -1478,6 +1480,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
nvgpu_clk_get_vbios_clk_domain_gp10x;
g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data =
clk_avfs_get_vin_cal_fuse_v10;
g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill =
nvgpu_clk_vf_change_inject_data_fill_gp10x;
break;
case APP_VERSION_GM20B:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size =

13
drivers/gpu/nvgpu/ctrl/ctrlclk.h
View File

@@ -176,6 +176,19 @@ struct ctrl_clk_clk_domain_list_item {
u8 target_regime_id;
};
struct ctrl_clk_clk_domain_list_item_v1 {
u32 clk_domain;
u32 clk_freq_khz;
u8 regime_id;
u8 source;
};
struct ctrl_clk_clk_domain_list {
u8 num_domains;
struct ctrl_clk_clk_domain_list_item_v1
clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
};
#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \
((pvfpair)->freq_mhz)

3
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -804,6 +804,9 @@ struct gpu_ops {
u32 (*clk_avfs_get_vin_cal_data)(struct gk20a *g,
struct avfsvinobjs *pvinobjs,
struct vin_device_v20 *pvindev);
u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g,
struct nv_pmu_clk_rpc *rpccall,
struct set_fll_clk *setfllclk);
}clk;
} pmu_ver;
struct {

27
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
View File

@@ -336,12 +336,24 @@ struct nv_pmu_clk_clk_domain_list {
NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
};
struct nv_pmu_clk_clk_domain_list_v1 {
u8 num_domains;
struct ctrl_clk_clk_domain_list_item_v1 clk_domains[
NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
};
struct nv_pmu_clk_vf_change_inject {
u8 flags;
struct nv_pmu_clk_clk_domain_list clk_list;
struct nv_pmu_volt_volt_rail_list volt_list;
};
struct nv_pmu_clk_vf_change_inject_v1 {
u8 flags;
struct nv_pmu_clk_clk_domain_list_v1 clk_list;
struct nv_pmu_volt_volt_rail_list_v1 volt_list;
};
#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002)
#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001)
@@ -400,12 +412,14 @@ union nv_pmu_clk_clk_freq_controller_boardobj_set_union {
NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller);
/* CLK CMD ID definitions. */
#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000)
#define NV_PMU_CLK_CMD_ID_RPC (0x00000001)
#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000001)
#define NV_PMU_CLK_CMD_ID_RPC (0x00000000)
#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
#define NV_PMU_CLK_RPC_ID_LOAD (0x00000002)
#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001)
#define NV_PMU_CLK_RPC_ID_LOAD (0x00000001)
#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000000)
#define NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG (0x00000002)
struct nv_pmu_clk_cmd_rpc {
u8 cmd_type;
@@ -432,13 +446,14 @@ struct nv_pmu_clk_rpc {
flcn_status flcn_status;
union {
struct nv_pmu_clk_vf_change_inject clk_vf_change_inject;
struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1;
struct nv_pmu_clk_load clk_load;
} params;
};
/* CLK MSG ID definitions */
#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000)
#define NV_PMU_CLK_MSG_ID_RPC (0x00000001)
#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000001)
#define NV_PMU_CLK_MSG_ID_RPC (0x00000000)
#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
struct nv_pmu_clk_msg_rpc {

2
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h
View File

@@ -343,7 +343,7 @@ struct nv_pmu_volt_volt_rail_list {
rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
};
struct nv_pmu_volt_volt_rail_list_V1 {
struct nv_pmu_volt_volt_rail_list_v1 {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item_v1
rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];