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gpu: nvgpu: Move FB MMU query to FB HAL

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Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count
instead of reading the number of LTCs from FB. These changes together
remove last direct uses of FB registers from GR.

JIRA NVGPU-714

Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1773076
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-07-06 12:37:10 -07:00
committed by mobile promotions
parent da03aa7825
commit 876953fbb8
10 changed files with 57 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -505,6 +505,10 @@ struct gpu_ops {
void (*init_kind_attr)(struct gk20a *g);
void (*set_mmu_page_size)(struct gk20a *g);
bool (*set_use_full_comp_tag_line)(struct gk20a *g);
u32 (*mmu_ctrl)(struct gk20a *g);
u32 (*mmu_debug_ctrl)(struct gk20a *g);
u32 (*mmu_debug_wr)(struct gk20a *g);
u32 (*mmu_debug_rd)(struct gk20a *g);
/*
* Compression tag line coverage. When mapping a compressible

20
drivers/gpu/nvgpu/gm20b/fb_gm20b.c
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@@ -68,6 +68,26 @@ bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g)
return true;
}
u32 gm20b_fb_mmu_ctrl(struct gk20a *g)
{
return gk20a_readl(g, fb_mmu_ctrl_r());
}
u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g)
{
return gk20a_readl(g, fb_mmu_debug_ctrl_r());
}
u32 gm20b_fb_mmu_debug_wr(struct gk20a *g)
{
return gk20a_readl(g, fb_mmu_debug_wr_r());
}
u32 gm20b_fb_mmu_debug_rd(struct gk20a *g)
{
return gk20a_readl(g, fb_mmu_debug_rd_r());
}
unsigned int gm20b_fb_compression_page_size(struct gk20a *g)
{
return SZ_128K;

4
drivers/gpu/nvgpu/gm20b/fb_gm20b.h
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@@ -29,6 +29,10 @@ struct gk20a;
void fb_gm20b_init_fs_state(struct gk20a *g);
void gm20b_fb_set_mmu_page_size(struct gk20a *g);
bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g);
u32 gm20b_fb_mmu_ctrl(struct gk20a *g);
u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g);
u32 gm20b_fb_mmu_debug_wr(struct gk20a *g);
u32 gm20b_fb_mmu_debug_rd(struct gk20a *g);
unsigned int gm20b_fb_compression_page_size(struct gk20a *g);
unsigned int gm20b_fb_compressible_page_size(struct gk20a *g);
u32 gm20b_fb_compression_align_mask(struct gk20a *g);

12
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
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@@ -36,7 +36,6 @@
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
#include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
#include <nvgpu/hw/gm20b/hw_ltc_gm20b.h>
#include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h>
@@ -49,7 +48,7 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g)
nvgpu_log_info(g, "initialize gpc mmu");
temp = gk20a_readl(g, fb_mmu_ctrl_r());
temp = g->ops.fb.mmu_ctrl(g);
temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() |
@@ -65,14 +64,13 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g)
gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
gk20a_readl(g, fb_mmu_debug_ctrl_r()));
g->ops.fb.mmu_debug_ctrl(g));
gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
gk20a_readl(g, fb_mmu_debug_wr_r()));
g->ops.fb.mmu_debug_wr(g));
gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
gk20a_readl(g, fb_mmu_debug_rd_r()));
g->ops.fb.mmu_debug_rd(g));
gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(),
gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(), g->ltc_count);
}
void gr_gm20b_bundle_cb_defaults(struct gk20a *g)

4
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
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@@ -340,6 +340,10 @@ static const struct gpu_ops gm20b_ops = {
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
.compression_page_size = gm20b_fb_compression_page_size,
.compressible_page_size = gm20b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,

4
drivers/gpu/nvgpu/gp106/hal_gp106.c
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@@ -411,6 +411,10 @@ static const struct gpu_ops gp106_ops = {
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,

4
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
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@@ -374,6 +374,10 @@ static const struct gpu_ops gp10b_ops = {
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,

4
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -461,6 +461,10 @@ static const struct gpu_ops gv100_ops = {
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,

9
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -57,7 +57,6 @@
#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
#define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100
@@ -4248,7 +4247,7 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
nvgpu_log_info(g, "initialize gpc mmu");
temp = gk20a_readl(g, fb_mmu_ctrl_r());
temp = g->ops.fb.mmu_ctrl(g);
temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
gr_gpcs_pri_mmu_ctrl_vol_fault_m() |
@@ -4269,11 +4268,11 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
gk20a_readl(g, fb_mmu_debug_ctrl_r()));
g->ops.fb.mmu_debug_ctrl(g));
gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
gk20a_readl(g, fb_mmu_debug_wr_r()));
g->ops.fb.mmu_debug_wr(g));
gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
gk20a_readl(g, fb_mmu_debug_rd_r()));
g->ops.fb.mmu_debug_rd(g));
}
int gr_gv11b_init_preemption_state(struct gk20a *g)

4
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -429,6 +429,10 @@ static const struct gpu_ops gv11b_ops = {
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
.mmu_debug_wr = gm20b_fb_mmu_debug_wr,
.mmu_debug_rd = gm20b_fb_mmu_debug_rd,
.compression_page_size = gp10b_fb_compression_page_size,
.compressible_page_size = gp10b_fb_compressible_page_size,
.compression_align_mask = gm20b_fb_compression_align_mask,