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gpu: nvgpu: Fix MISRA 11.8 violations in nvlink

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MISRA rule 11.8 prohibits any cast which removes "const" or "volatile"
qualification from the type pointed to by the pointer. Fix such 11.8
violations in nvlink code by adding "const" to type cast.

JIRA NVGPU-1921

Change-Id: Ib37617d7a0e08b22aaf1b865ba08fc0d803e3acc
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024903
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2019-02-21 17:06:37 +05:30
committed by mobile promotions
parent 4eca351622
commit 87cea7e409
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c
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@@ -120,18 +120,18 @@ static const struct nvlink_reginit nvlink_reginit_per_link_gpu[] = {
};
static int gv100_nvlink_get_tlc_reginit(enum nvgpu_nvlink_endp endp,
struct nvlink_reginit **reg, u32 *count)
const struct nvlink_reginit **reg, u32 *count)
{
int ret = 0;
switch(endp) {
case nvgpu_nvlink_endp_tegra:
*reg = (struct nvlink_reginit *)
*reg = (const struct nvlink_reginit *)
nvlink_reginit_per_link_tegra;
*count = (u32)ARRAY_SIZE(nvlink_reginit_per_link_tegra);
break;
case nvgpu_nvlink_endp_gpu:
*reg = (struct nvlink_reginit *)
*reg = (const struct nvlink_reginit *)
nvlink_reginit_per_link_gpu;
*count = (u32)ARRAY_SIZE(nvlink_reginit_per_link_gpu);
break;
@@ -147,7 +147,7 @@ int gv100_nvlink_reg_init(struct gk20a *g)
{
u32 i = 0;
u32 count = 0;
struct nvlink_reginit *reg;
const struct nvlink_reginit *reg;
enum nvgpu_nvlink_endp endp;
int err;
u32 link_id;