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gpu:nvgpu:fix powergate disabling order

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ELPG has to disabled before we write to clock gating registers
If ELPG is engaged during clock gating register write it will
cause error in ELPG engine

Bug 200013495
Bug 200014542

Change-Id: I57d1c59fc9311686829d898faddc90149df4cb46
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/432117
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
This commit is contained in:
Vijayakumar
2014-06-27 14:50:31 +05:30
committed by Dan Willemsen
parent e0d7e42e8c
commit 88c6d2fb21
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
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@@ -576,6 +576,8 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
if (err)
return -EPERM;
/*do elpg disable before clock gating */
gk20a_pmu_disable_elpg(g);
g->ops.clock_gating.slcg_gr_load_gating_prod(g,
false);
g->ops.clock_gating.slcg_perf_load_gating_prod(g,
@@ -586,7 +588,6 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A);
gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A);
gk20a_pmu_disable_elpg(g);
}
dbg_s->is_pg_disabled = true;