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gpu: nvgpu: Refacotor clk_domain Unit
As a part of refactoring this patch does the following *Move local struct to unit specific header file *Move nvgpu_pmu_clk_domain_freq_to_volt from clk.c to clk_domain.c *Move PMU specific struct to ucode_clk_inf.h *Merge content from nvgpu/clk.h to pmu/clk/clk.h *Update yaml file This will help to have arch consistency across all units. Change-Id: Ied5c6ee637e7fd5bbdee3f5bc3f6cf216454428a Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333366 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
committed by
Alex Waterman
Alex Waterman
parent
f0896f94e1
commit
88d3640bc5
@@ -1,43 +0,0 @@
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_INCLUDE_CLK_H
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#define NVGPU_INCLUDE_CLK_H
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#define CLK_NAME_MAX 24
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#define CLK_MAX_CNTRL_REGISTERS 2
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struct namemap_cfg {
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u32 namemap;
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u32 is_enable; /* Namemap enabled */
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u32 is_counter; /* Using cntr */
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struct gk20a *g;
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struct {
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u32 reg_ctrl_addr;
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u32 reg_ctrl_idx;
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u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS];
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} cntr;
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u32 scale;
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char name[CLK_NAME_MAX];
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};
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#endif /* NVGPU_INCLUDE_CLK_H */
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@@ -33,51 +33,49 @@
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/*!
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* Valid global VIN ID values
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*/
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#define CTRL_CLK_VIN_ID_SYS 0x00000000U
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#define CTRL_CLK_VIN_ID_LTC 0x00000001U
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#define CTRL_CLK_VIN_ID_XBAR 0x00000002U
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#define CTRL_CLK_VIN_ID_GPC0 0x00000003U
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#define CTRL_CLK_VIN_ID_GPC1 0x00000004U
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#define CTRL_CLK_VIN_ID_GPC2 0x00000005U
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#define CTRL_CLK_VIN_ID_GPC3 0x00000006U
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#define CTRL_CLK_VIN_ID_GPC4 0x00000007U
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#define CTRL_CLK_VIN_ID_GPC5 0x00000008U
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#define CTRL_CLK_VIN_ID_GPCS 0x00000009U
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#define CTRL_CLK_VIN_ID_SRAM 0x0000000AU
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#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FFU
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#define CTRL_CLK_VIN_ID_SYS 0x00000000U
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#define CTRL_CLK_VIN_ID_LTC 0x00000001U
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#define CTRL_CLK_VIN_ID_XBAR 0x00000002U
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#define CTRL_CLK_VIN_ID_GPC0 0x00000003U
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#define CTRL_CLK_VIN_ID_GPC1 0x00000004U
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#define CTRL_CLK_VIN_ID_GPC2 0x00000005U
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#define CTRL_CLK_VIN_ID_GPC3 0x00000006U
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#define CTRL_CLK_VIN_ID_GPC4 0x00000007U
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#define CTRL_CLK_VIN_ID_GPC5 0x00000008U
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#define CTRL_CLK_VIN_ID_GPCS 0x00000009U
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#define CTRL_CLK_VIN_ID_SRAM 0x0000000AU
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#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FFU
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#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000U
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#define CTRL_CLK_VIN_TYPE_V20 0x00000002U
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#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000U
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#define CTRL_CLK_VIN_TYPE_V20 0x00000002U
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/* valid clock domain values */
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#define CTRL_CLK_DOMAIN_MCLK (0x00000010U)
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#define CTRL_CLK_DOMAIN_HOSTCLK (0x00000020U)
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#define CTRL_CLK_DOMAIN_DISPCLK (0x00000040U)
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#define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000U)
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#define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000U)
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#define CTRL_CLK_DOMAIN_SYS2CLK (0x00800000U)
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#define CTRL_CLK_DOMAIN_HUB2CLK (0x01000000U)
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#define CTRL_CLK_DOMAIN_UTILSCLK (0x00040000U)
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#define CTRL_CLK_DOMAIN_PWRCLK (0x00080000U)
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#define CTRL_CLK_DOMAIN_NVDCLK (0x00100000U)
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#define CTRL_CLK_DOMAIN_PCIEGENCLK (0x00200000U)
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#define CTRL_CLK_DOMAIN_XCLK (0x04000000U)
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#define CTRL_CLK_DOMAIN_NVL_COMMON (0x08000000U)
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#define CTRL_CLK_DOMAIN_PEX_REFCLK (0x10000000U)
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#define CTRL_CLK_DOMAIN_GPCCLK (0x00000001U)
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#define CTRL_CLK_DOMAIN_XBARCLK (0x00000002U)
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#define CTRL_CLK_DOMAIN_SYSCLK (0x00000004U)
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#define CTRL_CLK_DOMAIN_HUBCLK (0x00000008U)
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#define CTRL_CLK_DOMAIN_MCLK 0x00000010U
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#define CTRL_CLK_DOMAIN_HOSTCLK 0x00000020U
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#define CTRL_CLK_DOMAIN_DISPCLK 0x00000040U
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#define CTRL_CLK_DOMAIN_GPC2CLK 0x00010000U
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#define CTRL_CLK_DOMAIN_XBAR2CLK 0x00040000U
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#define CTRL_CLK_DOMAIN_SYS2CLK 0x00800000U
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#define CTRL_CLK_DOMAIN_HUB2CLK 0x01000000U
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#define CTRL_CLK_DOMAIN_UTILSCLK 0x00040000U
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#define CTRL_CLK_DOMAIN_PWRCLK 0x00080000U
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#define CTRL_CLK_DOMAIN_NVDCLK 0x00100000U
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#define CTRL_CLK_DOMAIN_PCIEGENCLK 0x00200000U
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#define CTRL_CLK_DOMAIN_XCLK 0x04000000U
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#define CTRL_CLK_DOMAIN_NVL_COMMON 0x08000000U
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#define CTRL_CLK_DOMAIN_PEX_REFCLK 0x10000000U
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#define CTRL_CLK_DOMAIN_GPCCLK 0x00000001U
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#define CTRL_CLK_DOMAIN_XBARCLK 0x00000002U
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#define CTRL_CLK_DOMAIN_SYSCLK 0x00000004U
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#define CTRL_CLK_DOMAIN_HUBCLK 0x00000008U
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#define CTRL_CLK_FLL_REGIME_ID_INVALID ((u8)0x00000000)
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#define CTRL_CLK_FLL_REGIME_ID_FFR ((u8)0x00000001)
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#define CTRL_CLK_FLL_REGIME_ID_FR ((u8)0x00000002)
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#define CTRL_CLK_FLL_REGIME_ID_INVALID ((u8)0x00000000)
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#define CTRL_CLK_FLL_REGIME_ID_FFR ((u8)0x00000001)
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#define CTRL_CLK_FLL_REGIME_ID_FR ((u8)0x00000002)
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#define CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS 16
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#define CLK_CLOCK_MON_DOMAIN_COUNT 0x32U
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#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4U
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#define CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS 16
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#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4U
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/*
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* Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal
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*
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@@ -89,42 +87,43 @@
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* xbar2clk is 19 in Pascal and 14 in Volta
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* Changing for Pascal would break pwrclk of Volta
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*/
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#define CLKWHICH_GPCCLK 1U
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#define CLKWHICH_XBARCLK 2U
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#define CLKWHICH_SYSCLK 3U
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#define CLKWHICH_HUBCLK 4U
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#define CLKWHICH_MCLK 5U
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#define CLKWHICH_HOSTCLK 6U
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#define CLKWHICH_DISPCLK 7U
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#define CLKWHICH_XCLK 12U
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#define CLKWHICH_XBAR2CLK 14U
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#define CLKWHICH_SYS2CLK 15U
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#define CLKWHICH_HUB2CLK 16U
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#define CLKWHICH_GPC2CLK 17U
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#define CLKWHICH_PWRCLK 19U
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#define CLKWHICH_NVDCLK 20U
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#define CLKWHICH_PCIEGENCLK 26U
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#define CLKWHICH_GPCCLK 1U
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#define CLKWHICH_XBARCLK 2U
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#define CLKWHICH_SYSCLK 3U
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#define CLKWHICH_HUBCLK 4U
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#define CLKWHICH_MCLK 5U
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#define CLKWHICH_HOSTCLK 6U
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#define CLKWHICH_DISPCLK 7U
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#define CLKWHICH_XCLK 12U
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#define CLKWHICH_XBAR2CLK 14U
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#define CLKWHICH_SYS2CLK 15U
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#define CLKWHICH_HUB2CLK 16U
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#define CLKWHICH_GPC2CLK 17U
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#define CLKWHICH_PWRCLK 19U
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#define CLKWHICH_NVDCLK 20U
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#define CLKWHICH_PCIEGENCLK 26U
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/*!
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* Mask of all GPC VIN IDs supported by RM
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*/
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#define CTRL_CLK_LUT_NUM_ENTRIES_MAX (128U)
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#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x (128U)
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#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x (100U)
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#define CTRL_CLK_VIN_STEP_SIZE_UV (6250U)
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#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000U)
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#define CTRL_CLK_FLL_TYPE_DISABLED 0U
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#define CTRL_CLK_LUT_NUM_ENTRIES_MAX 128U
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#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x 128U
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#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x 100U
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#define CTRL_CLK_VIN_STEP_SIZE_UV 6250U
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#define CTRL_CLK_LUT_MIN_VOLTAGE_UV 450000U
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#define CTRL_CLK_FLL_TYPE_DISABLED 0U
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#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000U)
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#define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001U)
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#define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002U)
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#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC 0x00000000U
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#define CTRL_CLK_FLL_LUT_VSELECT_MIN 0x00000001U
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#define CTRL_CLK_FLL_LUT_VSELECT_SRAM 0x00000002U
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_HW_REQ (0x00000000U)
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_MIN (0x00000001U)
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_SW_REQ (0x00000003U)
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_HW_REQ 0x00000000U
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_MIN 0x00000001U
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_SW_REQ 0x00000003U
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#define CLK_CLOCK_MON_DOMAIN_COUNT 0x32U
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#define FREQ_STEP_SIZE_MHZ 15U
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#define FREQ_STEP_SIZE_MHZ 15U
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struct gk20a;
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struct clk_avfs_fll_objs;
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@@ -137,6 +136,21 @@ struct nvgpu_pmu_perf_change_input_clk_info;
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struct nvgpu_vin_device;
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struct nvgpu_clk_domain;
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struct nvgpu_clk_arb;
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struct nvgpu_clk_pmupstate;
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struct clk_domain_mon_status {
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u32 clk_api_domain;
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u32 low_threshold;
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u32 high_threshold;
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u32 clk_domain_fault_status;
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};
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struct clk_domains_mon_status_params {
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u32 clk_mon_domain_mask;
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struct clk_domain_mon_status
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clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
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};
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struct ctrl_clk_domain_clk_mon_item {
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u32 clk_api_domain;
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@@ -164,61 +178,6 @@ struct ctrl_clk_clk_domain_list {
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clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
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};
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struct clk_domain_mon_status {
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u32 clk_api_domain;
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u32 low_threshold;
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u32 high_threshold;
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u32 clk_domain_fault_status;
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};
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struct clk_domains_mon_status_params {
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u32 clk_mon_domain_mask;
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struct clk_domain_mon_status
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clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
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};
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struct ctrl_clk_vin_sw_override_list_item {
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u8 override_mode;
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u32 voltage_uV;
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};
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struct ctrl_clk_vin_sw_override_list {
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struct ctrl_boardobjgrp_mask_e32 volt_rails_mask;
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struct ctrl_clk_vin_sw_override_list_item
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volt[4];
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};
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union ctrl_clk_freq_delta_data {
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s32 delta_khz;
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s16 delta_percent;
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};
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struct ctrl_clk_freq_delta {
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u8 type;
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union ctrl_clk_freq_delta_data data;
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};
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struct ctrl_clk_clk_delta {
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struct ctrl_clk_freq_delta freq_delta;
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int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
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};
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struct nv_pmu_clk_lut_device_desc {
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u8 vselect_mode;
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u16 hysteresis_threshold;
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};
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struct nv_pmu_clk_regime_desc {
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u8 regime_id;
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u8 target_regime_id_override;
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u16 fixed_freq_regime_limit_mhz;
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};
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struct ctrl_clk_vf_pair {
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u16 freq_mhz;
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u32 voltage_uv;
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};
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struct nvgpu_set_fll_clk {
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u32 voltuv;
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u16 gpc2clkmhz;
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@@ -274,18 +233,6 @@ struct nvgpu_clk_pmupstate {
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typedef u32 vin_device_state_load(struct gk20a *g,
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struct nvgpu_clk_pmupstate *clk, struct nvgpu_vin_device *pdev);
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struct nvgpu_vin_device {
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struct boardobj super;
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u8 id;
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u8 volt_domain;
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u8 volt_domain_vbios;
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u8 por_override_mode;
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u8 override_mode;
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u32 flls_shared_mask;
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vin_device_state_load *state_load;
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};
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typedef int nvgpu_clkproglink(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
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struct nvgpu_clk_domain *pdomain);
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