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gpu: nvgpu: handle timestamp buffer full ctxsw_intr0

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If enabled, fecs trace updating happens from ucode
side even when there is no fecs trace dumper application
to consume it. Due to this, trace buffer will get
eventually full and ucode will trigger ctxsw_intr0.
Reset fecs_trace buffer to handle timestamp buffer full
ctxsw_intr0.

Bug 2361571
Bug 200472922

Change-Id: Ia26a17635fc6bd6e8663b8af983acc91839ecfcd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965370
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 790ba09554)
Reviewed-on: https://git-master.nvidia.com/r/1979746
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
This commit is contained in:
Seema Khowala
2018-12-04 10:41:19 -08:00
committed by mobile promotions
parent 8e2d0c7b3d
commit 89d5f40116
4 changed files with 24 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
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@@ -634,4 +634,12 @@ bool gk20a_fecs_trace_is_enabled(struct gk20a *g)
return (trace && nvgpu_thread_is_running(&trace->poll_task));
}
void gk20a_fecs_trace_reset_buffer(struct gk20a *g)
{
nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " ");
gk20a_fecs_trace_set_read_index(g,
gk20a_fecs_trace_get_write_index(g));
}
#endif /* CONFIG_GK20A_CTXSW_TRACE */

1
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h
View File

@@ -40,5 +40,6 @@ int gk20a_fecs_trace_enable(struct gk20a *g);
int gk20a_fecs_trace_disable(struct gk20a *g);
bool gk20a_fecs_trace_is_enabled(struct gk20a *g);
size_t gk20a_fecs_trace_buffer_size(struct gk20a *g);
void gk20a_fecs_trace_reset_buffer(struct gk20a *g);
#endif /* NVGPU_GK20A_FECS_TRACE_GK20A_H */

13
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -5308,9 +5308,20 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6));
nvgpu_err(g, "ctxsw intr0 set by ucode, error_code: 0x%08x",
if (mailbox_value == MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL) {
nvgpu_info(g, "ctxsw intr0 set by ucode, "
"timestamp buffer full");
#ifdef CONFIG_GK20A_CTXSW_TRACE
gk20a_fecs_trace_reset_buffer(g);
#else
ret = -1;
#endif
} else {
nvgpu_err(g,
"ctxsw intr0 set by ucode, error_code: 0x%08x",
mailbox_value);
ret = -1;
}
} else {
nvgpu_err(g,
"unhandled fecs error interrupt 0x%08x for channel %u",

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -69,6 +69,8 @@
#define CTXSW_INTR0 BIT32(0)
#define CTXSW_INTR1 BIT32(1)
#define MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL 0x26
struct tsg_gk20a;
struct channel_gk20a;
struct nvgpu_warpstate;