nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add handling for ctxsw_intr0

Browse Source 
ctxsw_intr0 is triggered by ucode even if it
is not enabled by driver. Add handling
for processing ctxsw_intr0. fecs mailbox(6)
is used to report fecs/gpccs misc error codes.
Also dump falcon stats for unhandled fecs intr.

Bug 2361571
Bug 200472922

Change-Id: Iefb3c0d46ad1d08db07fd3c08cff91a77835908c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966984
(cherry picked from commit 2c379cad0f
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/1979745
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2018-12-04 10:41:19 -08:00
committed by mobile promotions
parent 0d110b7522
commit 8e2d0c7b3d
3 changed files with 16 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -5304,10 +5304,18 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
nvgpu_err(g, "fecs watchdog triggered for channel %u, "
"cannot ctxsw anymore !!", isr_data->chid);
gk20a_fecs_dump_falcon_stats(g);
} else if ((gr_fecs_intr &
gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6));
nvgpu_err(g, "ctxsw intr0 set by ucode, error_code: 0x%08x",
mailbox_value);
ret = -1;
} else {
nvgpu_err(g,
"fecs error interrupt 0x%08x for channel %u",
gr_fecs_intr, isr_data->chid);
"unhandled fecs error interrupt 0x%08x for channel %u",
gr_fecs_intr, ch->chid);
gk20a_fecs_dump_falcon_stats(g);
}
gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);

3
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -66,6 +66,9 @@
#define NVGPU_PREEMPTION_MODE_COMPUTE_CTA (1 << 1)
#define NVGPU_PREEMPTION_MODE_COMPUTE_CILP (1 << 2)
#define CTXSW_INTR0 BIT32(0)
#define CTXSW_INTR1 BIT32(1)
struct tsg_gk20a;
struct channel_gk20a;
struct nvgpu_warpstate;

4
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -1996,7 +1996,9 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g,
* INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR)
* indicates that a CILP ctxsw save has finished
*/
if (gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) {
if ((gr_fecs_intr &
gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR1)) != 0U) {
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
"CILP: ctxsw save completed!\n");