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gpu: nvgpu: fix MISRA 15.7 errors in gr falcon

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Fixed issues related to no non-empty terminating
"else" statement.

JIRA NVGPU-3226

Change-Id: Iebb21ab0352bbdb02c44629f9cc7d06c75c11ab2
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110733
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-05-02 16:12:40 -07:00
committed by mobile promotions
parent fd79ecec05
commit 8a57a9d8f1
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c
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@@ -607,6 +607,8 @@ static int gm20b_gr_falcon_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
mailbox_id, reg);
g->ops.gr.falcon.dump_stats(g);
return -1;
} else {
nvgpu_log_info(g, "fecs mailbox return success");
}
nvgpu_log_fn(g, "done");
@@ -1006,6 +1008,8 @@ u32 gm20b_gr_falcon_fecs_host_intr_status(struct gk20a *g,
} else if ((gr_fecs_intr &
gr_fecs_host_int_status_fault_during_ctxsw_f(1)) != 0U) {
fecs_host_intr->fault_during_ctxsw_active = true;
} else {
nvgpu_log_info(g, "un-handled fecs intr: 0x%x", gr_fecs_intr);
}
return gr_fecs_intr;