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gpu: nvgpu: gp10b: Use phys addresses in PDEs

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Use physical addresses in PDEs. All page table levels fit in 4k, so no
need for SMMU mapping.

Change-Id: Id9e418f35a79343f4a332a230e04abda5e0dd5d2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/783748
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
This commit is contained in:
Terje Bergstrom
2015-08-10 14:53:47 -07:00
committed by Deepak Nibade
parent b0667dcd8a
commit 8ae3f0ac28
1 changed files with 4 additions and 7 deletions
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11
drivers/gpu/nvgpu/gp10b/mm_gp10b.c
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@@ -160,13 +160,11 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
struct gk20a_mm_entry *pte = parent->entries + i;
u32 pde_v[2] = {0, 0};
u32 *pde;
struct gk20a *g = vm->mm->g;
gk20a_dbg_fn("");
pte_addr = g->ops.mm.get_iova_addr(g, pte->sgt->sgl, 0)
>> gmmu_new_pde_address_shift_v();
pde_addr = g->ops.mm.get_iova_addr(g, parent->sgt->sgl, 0);
pte_addr = sg_phys(pte->sgt->sgl) >> gmmu_new_pde_address_shift_v();
pde_addr = sg_phys(parent->sgt->sgl);
pde_v[0] |= gmmu_new_pde_aperture_video_memory_f();
pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
@@ -203,7 +201,6 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
struct gk20a_mm_entry *entry = pte->entries + i;
u32 pde_v[4] = {0, 0, 0, 0};
u32 *pde;
struct gk20a *g = vm->mm->g;
gk20a_dbg_fn("");
@@ -211,11 +208,11 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
big_valid = entry->size && entry->pgsz == gmmu_page_size_big;
if (small_valid)
pte_addr_small = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0)
pte_addr_small = sg_phys(entry->sgt->sgl)
>> gmmu_new_dual_pde_address_shift_v();
if (big_valid)
pte_addr_big = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0)
pte_addr_big = sg_phys(entry->sgt->sgl)
>> gmmu_new_dual_pde_address_big_shift_v();
if (small_valid) {