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gpu: nvgpu: Implement per-chip pagepool size

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Bug 1567274

Change-Id: Ib366f56c109f60be98435124e9e73697d161c4d0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606935
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Terje Bergstrom
2014-11-20 15:41:41 +02:00
committed by Dan Willemsen
parent bf9f5f82d1
commit 8af8c35741
4 changed files with 24 additions and 2 deletions
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1
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -143,6 +143,7 @@ struct gpu_ops {
struct zbc_entry *color_val, u32 index);
int (*add_zbc_depth)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index);
void (*buffer_size_defaults)(struct gk20a *g);
} gr;
const char *name;
struct {

14
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -858,7 +858,7 @@ static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g,
size = gr->global_ctx_buffer[PAGEPOOL].size /
gr_scc_pagepool_total_pages_byte_granularity_v();
if (size == gr_scc_pagepool_total_pages_hwmax_value_v())
if (size == gr->pagepool_default_size)
size = gr_scc_pagepool_total_pages_hwmax_v();
gk20a_dbg_info("pagepool buffer addr : 0x%016llx, size : %d",
@@ -2301,7 +2301,7 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g)
u32 cb_buffer_size = gr->bundle_cb_default_size *
gr_scc_bundle_cb_size_div_256b_byte_granularity_v();
u32 pagepool_buffer_size = gr_scc_pagepool_total_pages_hwmax_value_v() *
u32 pagepool_buffer_size = gr->pagepool_default_size *
gr_scc_pagepool_total_pages_byte_granularity_v();
gk20a_dbg_fn("");
@@ -3187,6 +3187,7 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
g->ops.gr.bundle_cb_defaults(g);
g->ops.gr.cb_size_default(g);
g->ops.gr.calc_global_ctx_buffer_size(g);
g->ops.gr.buffer_size_defaults(g);
gr->timeslice_mode = gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v();
gk20a_dbg_info("bundle_cb_default_size: %d",
@@ -7317,6 +7318,14 @@ void gk20a_resume_all_sms(struct gk20a *g)
gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0);
}
static void gr_gk20a_buffer_size_defaults(struct gk20a *g)
{
g->gr.pagepool_default_size =
gr_scc_pagepool_total_pages_hwmax_value_v();
g->gr.pagepool_max_size =
gr_scc_pagepool_total_pages_hwmax_value_v();
}
void gk20a_init_gr_ops(struct gpu_ops *gops)
{
gops->gr.access_smpc_reg = gr_gk20a_access_smpc_reg;
@@ -7353,5 +7362,6 @@ void gk20a_init_gr_ops(struct gpu_ops *gops)
gops->gr.detect_sm_arch = gr_gk20a_detect_sm_arch;
gops->gr.add_zbc_color = gr_gk20a_add_zbc_color;
gops->gr.add_zbc_depth = gr_gk20a_add_zbc_depth;
gops->gr.buffer_size_defaults = gr_gk20a_buffer_size_defaults;
}

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -243,6 +243,8 @@ struct gr_gk20a {
u32 alpha_cb_default_size;
u32 alpha_cb_size;
u32 timeslice_mode;
u32 pagepool_default_size;
u32 pagepool_max_size;
struct gr_ctx_buffer_desc global_ctx_buffer[NR_GLOBAL_CTX_BUF];

9
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -770,6 +770,14 @@ static void gr_gm20b_detect_sm_arch(struct gk20a *g)
gr_gpc0_tpc0_sm_arch_warp_count_v(v);
}
static void gr_gm20b_buffer_size_defaults(struct gk20a *g)
{
g->gr.pagepool_default_size =
gr_scc_pagepool_total_pages_hwmax_value_v();
g->gr.pagepool_max_size =
gr_scc_pagepool_total_pages_hwmax_value_v();
}
void gm20b_init_gr(struct gpu_ops *gops)
{
gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu;
@@ -807,4 +815,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
gops->gr.detect_sm_arch = gr_gm20b_detect_sm_arch;
gops->gr.add_zbc_color = gr_gk20a_add_zbc_color;
gops->gr.add_zbc_depth = gr_gk20a_add_zbc_depth;
gops->gr.buffer_size_defaults = gr_gm20b_buffer_size_defaults;
}