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gpu: nvgpu: restructure sync cmdbufs specific gpu_ops

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sync cmbbuf specific ops pointers are moved into a new struct sync_ops
under the parent struct gpu_ops. The HAL assignments to the gk20a and
gv11b versions are updated to match the new struct type.

Jira NVGPU-1308

Change-Id: I1d9832ed5e938cb65747f0f6d34088552f75e2bc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975919
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2018-12-19 11:26:45 +05:30
committed by mobile promotions
parent 6a31f02a2d
commit 8b57b3b938
11 changed files with 121 additions and 96 deletions
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7
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -404,6 +404,10 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.channel_resume = gk20a_channel_resume,
.set_error_notifier = nvgpu_set_error_notifier,
.setup_sw = gk20a_init_fifo_setup_sw,
.resetup_ramfc = NULL,
.set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask,
},
.sync = {
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
@@ -415,11 +419,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
.get_sync_ro_map = NULL,
#endif
.resetup_ramfc = NULL,
.get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size,
.add_sema_cmd = gk20a_fifo_add_sema_cmd,
.set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask,
},
.runlist = {
.reschedule_runlist = NULL,
@@ -659,6 +661,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
gops->clock_gating = vgpu_gp10b_ops.clock_gating;
gops->fifo = vgpu_gp10b_ops.fifo;
gops->runlist = vgpu_gp10b_ops.runlist;
gops->sync = vgpu_gp10b_ops.sync;
gops->netlist = vgpu_gp10b_ops.netlist;
#ifdef CONFIG_GK20A_CTXSW_TRACE
gops->fecs_trace = vgpu_gp10b_ops.fecs_trace;

17
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -477,6 +477,15 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.channel_resume = gk20a_channel_resume,
.set_error_notifier = nvgpu_set_error_notifier,
.setup_sw = gk20a_init_fifo_setup_sw,
.resetup_ramfc = NULL,
.free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
.ring_channel_doorbell = gv11b_ring_channel_doorbell,
.set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask,
.usermode_base = gv11b_fifo_usermode_base,
.doorbell_token = gv11b_fifo_doorbell_token,
},
.sync = {
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
.free_syncpt_buf = vgpu_gv11b_fifo_free_syncpt_buf,
@@ -488,16 +497,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
.get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map,
#endif
.resetup_ramfc = NULL,
.free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
.ring_channel_doorbell = gv11b_ring_channel_doorbell,
.get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_fifo_add_sema_cmd,
.set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask,
.usermode_base = gv11b_fifo_usermode_base,
.doorbell_token = gv11b_fifo_doorbell_token,
},
.runlist = {
.reschedule_runlist = NULL,
@@ -736,6 +738,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
gops->clock_gating = vgpu_gv11b_ops.clock_gating;
gops->fifo = vgpu_gv11b_ops.fifo;
gops->runlist = vgpu_gv11b_ops.runlist;
gops->sync = vgpu_gv11b_ops.sync;
gops->netlist = vgpu_gv11b_ops.netlist;
gops->mm = vgpu_gv11b_ops.mm;
#ifdef CONFIG_GK20A_CTXSW_TRACE