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gpu: nvgpu: add sw method for SHADER_CUT_COLLECTOR

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Added sw method for NVC397_SET_SHADER_CUT_COLLECTOR
to enable/disable SHADER_CUT_COLLECTOR_STATE.

Added support for this sw method in gv11b and gv100.

Bug 2108381

Change-Id: Ief2c2bf5d9c99779dad3b1243041c5efe56287d3
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1703662
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2018-04-26 18:33:06 -07:00
committed by mobile promotions
parent c9463fdbb3
commit 8b666b0bd6
4 changed files with 50 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1202,6 +1202,25 @@ static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data)
}
}
static void gr_gv11b_set_shader_cut_collector(struct gk20a *g, u32 data)
{
u32 val;
nvgpu_log_fn(g, "gr_gv11b_set_shader_cut_collector");
val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r());
if (data & NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE)
val = set_field(val,
gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(),
gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f());
else
val = set_field(val,
gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(),
gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f());
gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val);
}
int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data)
{
@@ -1249,6 +1268,9 @@ int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
case NVC397_SET_BES_CROP_DEBUG4:
g->ops.gr.set_bes_crop_debug4(g, data);
break;
case NVC397_SET_SHADER_CUT_COLLECTOR:
gr_gv11b_set_shader_cut_collector(g, data);
break;
default:
goto fail;
}

4
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -63,6 +63,7 @@ enum {
#define NVC397_SET_SKEDCHECK 0x10c0
#define NVC397_SET_BES_CROP_DEBUG3 0x10c4
#define NVC397_SET_BES_CROP_DEBUG4 0x10b0
#define NVC397_SET_SHADER_CUT_COLLECTOR 0x10c8
#define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1
#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2
@@ -73,6 +74,9 @@ enum {
#define NVC397_SET_SKEDCHECK_18_DISABLE 0x1
#define NVC397_SET_SKEDCHECK_18_ENABLE 0x2
#define NVC397_SET_SHADER_CUT_COLLECTOR_STATE_DISABLE 0x0
#define NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE 0x1
#define NVC3C0_SET_SKEDCHECK 0x23c
#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0

12
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
View File

@@ -3884,6 +3884,18 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
{
return 0x1U << 10U;
}
static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void)
{
return 0x1U << 28U;
}
static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void)
{
return 0x0U;
}
static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void)
{
return 0x10000000U;
}
static inline u32 gr_fe_pwr_mode_r(void)
{
return 0x00404170U;

12
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
View File

@@ -4640,6 +4640,18 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
{
return 0x1U << 10U;
}
static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void)
{
return 0x1U << 28U;
}
static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void)
{
return 0x0U;
}
static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void)
{
return 0x10000000U;
}
static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void)
{
return 0x00584200U;