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gpu: nvgpu: fix init msg param handing

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bug 1809509

latest pmu now returns information about 3 queues
only. nvgpu pmu driver still support 5 queues to
be compatible with older firmware. handling this
properly

Change-Id: I4bc166712465f4b52537c97e6d254760c59e0d16
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1215533
(cherry picked from commit c7428c031a095b2d42512b7a8a0a9d818290e376)
Reviewed-on: http://git-master/r/1231040
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vijayakumar
2016-09-06 17:11:39 +05:30
committed by mobile promotions
parent 61f26b68f6
commit 8de7ea2543
2 changed files with 18 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
View File

@@ -1150,11 +1150,21 @@ static void get_pmu_init_msg_pmu_queue_params_v3(struct pmu_queue *queue,
(struct pmu_init_msg_pmu_v3 *)pmu_init_msg;
u32 current_ptr = 0;
u8 i;
queue->index = init->queue_index[id];
queue->size = init->queue_size[id];
if (id != 0) {
for ( i = 0 ; i < id; i++)
current_ptr += init->queue_size[i];
u8 tmp_id = id;
if (tmp_id == PMU_COMMAND_QUEUE_HPQ)
tmp_id = PMU_QUEUE_HPQ_IDX_FOR_V3;
else if (tmp_id == PMU_COMMAND_QUEUE_LPQ)
tmp_id = PMU_QUEUE_LPQ_IDX_FOR_V3;
else if (tmp_id == PMU_MESSAGE_QUEUE)
tmp_id = PMU_QUEUE_MSG_IDX_FOR_V3;
else
return;
queue->index = init->queue_index[tmp_id];
queue->size = init->queue_size[tmp_id];
if (tmp_id != 0) {
for (i = 0 ; i < tmp_id; i++)
current_ptr += init->queue_size[i];
}
queue->offset = init->queue_offset + current_ptr;
}
@@ -2435,7 +2445,6 @@ static int pmu_queue_init(struct pmu_gk20a *pmu,
struct pmu_queue *queue = &pmu->queue[id];
queue->id = id;
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params(queue, id, init);
queue->mutex_id = id;
mutex_init(&queue->mutex);

3
drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
View File

@@ -256,6 +256,9 @@ struct pmu_init_msg_pmu_v2 {
};
#define PMU_QUEUE_COUNT_FOR_V3 3
#define PMU_QUEUE_HPQ_IDX_FOR_V3 0
#define PMU_QUEUE_LPQ_IDX_FOR_V3 1
#define PMU_QUEUE_MSG_IDX_FOR_V3 2
struct pmu_init_msg_pmu_v3 {
u8 msg_type;
u8 queue_index[PMU_QUEUE_COUNT_FOR_V3];