gpu: nvgpu: add ramfc specific pbdma hal functions

Only one h/w header is allowed per hal file. ramfc_*.c uses both
hw_ramfc_*.h and hw_pbdma_*.h. The pbdma dependencies are removed from
the HAL unit of ramfc by constructing new HAL functions for pbdma unit.
The HAL ops functions added are listed below.

get_gp_base
get_gp_base_hi
get_fc_formats
get_fc_pb_header
get_fc_subdevice
get_fc_target
get_ctrl_hce_priv_mode_yes
get_userd_aperture_mask
get_userd_addr
get_userd_hi_addr
get_fc_runlist_timeslice
get_config_auth_level_privileged
set_channel_info_veid
config_userd_writeback_enable
allowed_syncpoints_0_index_f
allowed_syncpoints_0_valid_f
allowed_syncpoints_0_index_v

These HAL ops uses the following new implementations.

gm20b_pbdma_get_gp_base
gm20b_pbdma_get_gp_base_hi
gm20b_pbdma_get_fc_formats
gm20b_pbdma_get_fc_pb_header
gm20b_pbdma_get_fc_subdevice
gm20b_pbdma_get_fc_target
gm20b_pbdma_get_ctrl_hce_priv_mode_yes
gm20b_pbdma_get_userd_aperture_mask
gm20b_pbdma_get_userd_addr
gm20b_pbdma_get_userd_hi_addr

gp10b_pbdma_get_fc_runlist_timeslice
gp10b_pbdma_get_config_auth_level_privileged
gp10b_pbdma_allowed_syncpoints_0_index_f
gp10b_pbdma_allowed_syncpoints_0_valid_f
gp10b_pbdma_allowed_syncpoints_0_index_v

gv11b_pbdma_get_fc_pb_header
gv11b_pbdma_get_fc_target
gv11b_pbdma_set_channel_info_veid
gv11b_pbdma_config_userd_writeback_enable

Jira NVGPU-3195

Change-Id: I849f16650046eca38c67b0d6e0e43cd2ab1ac224
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102576
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gv11b/fifo_gv11b.h

@@ -25,8 +25,6 @@
 #ifndef FIFO_GV11B_H
 #define FIFO_GV11B_H
 
-#define PBDMA_SUBDEVICE_ID  1U
-
 #define CHANNEL_INFO_VEID0		0U
 
 struct gpu_ops;

drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c

@@ -21,6 +21,8 @@
  */
 
 #include <nvgpu/log.h>
+#include <nvgpu/log2.h>
+#include <nvgpu/utils.h>
 #include <nvgpu/io.h>
 #include <nvgpu/bitops.h>
 #include <nvgpu/bug.h>
@@ -35,6 +37,8 @@
 
 #include "pbdma_gm20b.h"
 
+#define PBDMA_SUBDEVICE_ID  1U
+
 static const char *const pbdma_intr_fault_type_desc[] = {
 	"MEMREQ timeout", "MEMACK_TIMEOUT", "MEMACK_EXTRA acks",
 	"MEMDAT_TIMEOUT", "MEMDAT_EXTRA acks", "MEMFLUSH noack",
@@ -507,3 +511,67 @@ void gm20b_pbdma_setup_hw(struct gk20a *g)
 		nvgpu_writel(g, pbdma_timeout_r(i), timeout);
 	}
 }
+
+u32 gm20b_pbdma_get_gp_base(u64 gpfifo_base)
+{
+	return pbdma_gp_base_offset_f(
+		u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()));
+}
+
+u32 gm20b_pbdma_get_gp_base_hi(u64 gpfifo_base, u32 gpfifo_entry)
+{
+	return 	(pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
+		pbdma_gp_base_hi_limit2_f((u32)ilog2(gpfifo_entry)));
+}
+
+u32 gm20b_pbdma_get_fc_formats(void)
+{
+	return	(pbdma_formats_gp_fermi0_f() | pbdma_formats_pb_fermi1_f() |
+			pbdma_formats_mp_fermi0_f());
+}
+
+u32 gm20b_pbdma_get_fc_pb_header(void)
+{
+	return (pbdma_pb_header_priv_user_f() |
+		pbdma_pb_header_method_zero_f() |
+		pbdma_pb_header_subchannel_zero_f() |
+		pbdma_pb_header_level_main_f() |
+		pbdma_pb_header_first_true_f() |
+		pbdma_pb_header_type_inc_f());
+}
+
+u32 gm20b_pbdma_get_fc_subdevice(void)
+{
+	return (pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) |
+		pbdma_subdevice_status_active_f() |
+		pbdma_subdevice_channel_dma_enable_f());
+}
+
+u32 gm20b_pbdma_get_fc_target(void)
+{
+	return pbdma_target_engine_sw_f();
+}
+
+u32 gm20b_pbdma_get_ctrl_hce_priv_mode_yes(void)
+{
+	return pbdma_hce_ctrl_hce_priv_mode_yes_f();
+}
+
+u32 gm20b_pbdma_get_userd_aperture_mask(struct gk20a *g,
+		struct nvgpu_mem *mem)
+{
+	return	(nvgpu_aperture_mask(g, mem,
+			pbdma_userd_target_sys_mem_ncoh_f(),
+			pbdma_userd_target_sys_mem_coh_f(),
+			pbdma_userd_target_vid_mem_f()));
+}
+
+u32 gm20b_pbdma_get_userd_addr(u32 addr_lo)
+{
+	return pbdma_userd_addr_f(addr_lo);
+}
+
+u32 gm20b_pbdma_get_userd_hi_addr(u32 addr_hi)
+{
+	return pbdma_userd_hi_addr_f(addr_hi);
+}

drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h

@@ -61,4 +61,15 @@ void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
 		     struct nvgpu_channel_dump_info *info);
 void gm20b_pbdma_setup_hw(struct gk20a *g);
 
+u32 gm20b_pbdma_get_gp_base(u64 gpfifo_base);
+u32 gm20b_pbdma_get_gp_base_hi(u64 gpfifo_base, u32 gpfifo_entry);
+u32 gm20b_pbdma_get_fc_formats(void);
+u32 gm20b_pbdma_get_fc_pb_header(void);
+u32 gm20b_pbdma_get_fc_subdevice(void);
+u32 gm20b_pbdma_get_fc_target(void);
+u32 gm20b_pbdma_get_ctrl_hce_priv_mode_yes(void);
+u32 gm20b_pbdma_get_userd_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem);
+u32 gm20b_pbdma_get_userd_addr(u32 addr_lo);
+u32 gm20b_pbdma_get_userd_hi_addr(u32 addr_hi);
+
 #endif /* NVGPU_PBDMA_GM20B_H */

drivers/gpu/nvgpu/hal/fifo/pbdma_gp10b.c

@@ -55,4 +55,31 @@ u32 gp10b_pbdma_channel_fatal_0_intr_descs(void)
 		pbdma_intr_0_signature_pending_f();
 
 	return channel_fatal_0_intr_descs;
+}
+
+u32 gp10b_pbdma_get_fc_runlist_timeslice(void)
+{
+	return (pbdma_runlist_timeslice_timeout_128_f() |
+		pbdma_runlist_timeslice_timescale_3_f() |
+		pbdma_runlist_timeslice_enable_true_f());
+}
+
+u32 gp10b_pbdma_get_config_auth_level_privileged(void)
+{
+	return pbdma_config_auth_level_privileged_f();
+}
+
+u32 gp10b_pbdma_allowed_syncpoints_0_index_f(u32 syncpt)
+{
+	return pbdma_allowed_syncpoints_0_index_f(syncpt);
+}
+
+u32 gp10b_pbdma_allowed_syncpoints_0_valid_f(void)
+{
+	return pbdma_allowed_syncpoints_0_valid_f(1);
+}
+
+u32 gp10b_pbdma_allowed_syncpoints_0_index_v(u32 offset)
+{
+	return pbdma_allowed_syncpoints_0_index_v(offset);
 }

drivers/gpu/nvgpu/hal/fifo/pbdma_gp10b.h

@@ -29,5 +29,10 @@ struct gk20a;
 
 u32 gp10b_pbdma_get_signature(struct gk20a *g);
 u32 gp10b_pbdma_channel_fatal_0_intr_descs(void);
+u32 gp10b_pbdma_get_fc_runlist_timeslice(void);
+u32 gp10b_pbdma_get_config_auth_level_privileged(void);
+u32 gp10b_pbdma_allowed_syncpoints_0_index_f(u32 syncpt);
+u32 gp10b_pbdma_allowed_syncpoints_0_valid_f(void);
+u32 gp10b_pbdma_allowed_syncpoints_0_index_v(u32 offset);
 
 #endif /* NVGPU_PBDMA_GP10B_H */

drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.c

@@ -253,3 +253,29 @@ void gv11b_pbdma_setup_hw(struct gk20a *g)
 		}
 	}
 }
+
+u32 gv11b_pbdma_get_fc_pb_header(void)
+{
+	return (pbdma_pb_header_method_zero_f() |
+		pbdma_pb_header_subchannel_zero_f() |
+		pbdma_pb_header_level_main_f() |
+		pbdma_pb_header_first_true_f() |
+		pbdma_pb_header_type_inc_f());
+}
+
+u32 gv11b_pbdma_get_fc_target(void)
+{
+	return (gm20b_pbdma_get_fc_target() |
+			pbdma_target_eng_ctx_valid_true_f() |
+			pbdma_target_ce_ctx_valid_true_f());
+}
+
+u32 gv11b_pbdma_set_channel_info_veid(u32 channel_id)
+{
+	return pbdma_set_channel_info_veid_f(channel_id);
+}
+
+u32 gv11b_pbdma_config_userd_writeback_enable(void)
+{
+	return pbdma_config_userd_writeback_enable_f();
+}

drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h

@@ -34,5 +34,9 @@ bool gv11b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0,
 bool gv11b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
 			u32 *error_notifier);
 u32 gv11b_pbdma_channel_fatal_0_intr_descs(void);
+u32 gv11b_pbdma_get_fc_pb_header(void);
+u32 gv11b_pbdma_get_fc_target(void);
+u32 gv11b_pbdma_set_channel_info_veid(u32 channel_id);
+u32 gv11b_pbdma_config_userd_writeback_enable(void);
 
 #endif /* NVGPU_PBDMA_GV11B_H */

drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c

@@ -30,7 +30,6 @@
 #include "ramfc_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 
 int gk20a_ramfc_commit_userd(struct channel_gk20a *ch)
@@ -49,15 +48,12 @@ int gk20a_ramfc_commit_userd(struct channel_gk20a *ch)
 
 	nvgpu_mem_wr32(g, &ch->inst_block,
 		ram_in_ramfc_w() + ram_fc_userd_w(),
-		nvgpu_aperture_mask(g, ch->userd_mem,
-			pbdma_userd_target_sys_mem_ncoh_f(),
-			pbdma_userd_target_sys_mem_coh_f(),
-			pbdma_userd_target_vid_mem_f()) |
-		pbdma_userd_addr_f(addr_lo));
+		g->ops.pbdma.get_userd_aperture_mask(g, ch->userd_mem) |
+		g->ops.pbdma.get_userd_addr(addr_lo));
 
 	nvgpu_mem_wr32(g, &ch->inst_block,
 		ram_in_ramfc_w() + ram_fc_userd_hi_w(),
-		pbdma_userd_hi_addr_f(addr_hi));
+		g->ops.pbdma.get_userd_hi_addr(addr_hi));
 
 	return 0;
 }
@@ -67,47 +63,31 @@ int gk20a_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
 {
 	struct gk20a *g = ch->g;
 	struct nvgpu_mem *mem = &ch->inst_block;
-	unsigned long limit2_val;
 
 	nvgpu_log_fn(g, " ");
 
 	nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
-		pbdma_gp_base_offset_f(
-		u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
+		g->ops.pbdma.get_gp_base(gpfifo_base));
 
-	limit2_val = ilog2(gpfifo_entries);
-	if (u64_hi32(limit2_val) != 0U) {
-		nvgpu_err(g,  "Unable to cast pbdma limit2 value");
-		return -EOVERFLOW;
-	}
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
-		pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
-		pbdma_gp_base_hi_limit2_f((u32)limit2_val));
+		g->ops.pbdma.get_gp_base_hi(gpfifo_base, gpfifo_entries));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
 		 ch->g->ops.pbdma.get_signature(ch->g));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_formats_w(),
-		pbdma_formats_gp_fermi0_f() |
-		pbdma_formats_pb_fermi1_f() |
-		pbdma_formats_mp_fermi0_f());
+		g->ops.pbdma.get_fc_formats());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
-		pbdma_pb_header_priv_user_f() |
-		pbdma_pb_header_method_zero_f() |
-		pbdma_pb_header_subchannel_zero_f() |
-		pbdma_pb_header_level_main_f() |
-		pbdma_pb_header_first_true_f() |
-		pbdma_pb_header_type_inc_f());
+		g->ops.pbdma.get_fc_pb_header());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(),
-		pbdma_subdevice_id_f(1) |
-		pbdma_subdevice_status_active_f() |
-		pbdma_subdevice_channel_dma_enable_f());
+		g->ops.pbdma.get_fc_subdevice());
 
-	nvgpu_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f());
+	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
+		g->ops.pbdma.get_fc_target());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
 		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
@@ -127,7 +107,7 @@ int gk20a_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
 	if (ch->is_privileged_channel) {
 		/* Enable HCE priv mode for phys mode transfer */
 		nvgpu_mem_wr32(g, mem, ram_fc_hce_ctrl_w(),
-		pbdma_hce_ctrl_hce_priv_mode_yes_f());
+		g->ops.pbdma.get_ctrl_hce_priv_mode_yes());
 	}
 
 	return g->ops.ramfc.commit_userd(ch);

drivers/gpu/nvgpu/hal/fifo/ramfc_gp10b.c

@@ -32,7 +32,6 @@
 #include "hal/fifo/ramfc_gk20a.h"
 #include "hal/fifo/ramfc_gp10b.h"
 
-#include <nvgpu/hw/gp10b/hw_pbdma_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
 
 int gp10b_ramfc_commit_userd(struct channel_gk20a *ch)
@@ -51,15 +50,12 @@ int gp10b_ramfc_commit_userd(struct channel_gk20a *ch)
 
 	nvgpu_mem_wr32(g, &ch->inst_block,
 		ram_in_ramfc_w() + ram_fc_userd_w(),
-		nvgpu_aperture_mask(g, ch->userd_mem,
-			pbdma_userd_target_sys_mem_ncoh_f(),
-			pbdma_userd_target_sys_mem_coh_f(),
-			pbdma_userd_target_vid_mem_f()) |
-		pbdma_userd_addr_f(addr_lo));
+		g->ops.pbdma.get_userd_aperture_mask(g, ch->userd_mem) |
+		g->ops.pbdma.get_userd_addr(addr_lo));
 
 	nvgpu_mem_wr32(g, &ch->inst_block,
 		ram_in_ramfc_w() + ram_fc_userd_hi_w(),
-		pbdma_userd_hi_addr_f(addr_hi));
+		g->ops.pbdma.get_userd_hi_addr(addr_hi));
 
 	return 0;
 }
@@ -75,54 +71,42 @@ int gp10b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
 	nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
-		pbdma_gp_base_offset_f(
-			u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
+		g->ops.pbdma.get_gp_base(gpfifo_base));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
-		pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
-		pbdma_gp_base_hi_limit2_f((u32)ilog2(gpfifo_entries)));
+		g->ops.pbdma.get_gp_base_hi(gpfifo_base, gpfifo_entries));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
 		ch->g->ops.pbdma.get_signature(ch->g));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_formats_w(),
-		pbdma_formats_gp_fermi0_f() |
-		pbdma_formats_pb_fermi1_f() |
-		pbdma_formats_mp_fermi0_f());
+		g->ops.pbdma.get_fc_formats());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
-		pbdma_pb_header_priv_user_f() |
-		pbdma_pb_header_method_zero_f() |
-		pbdma_pb_header_subchannel_zero_f() |
-		pbdma_pb_header_level_main_f() |
-		pbdma_pb_header_first_true_f() |
-		pbdma_pb_header_type_inc_f());
+		g->ops.pbdma.get_fc_pb_header());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(),
-		pbdma_subdevice_id_f(1) |
-		pbdma_subdevice_status_active_f() |
-		pbdma_subdevice_channel_dma_enable_f());
+		g->ops.pbdma.get_fc_subdevice());
 
-	nvgpu_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f());
+	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
+		g->ops.pbdma.get_fc_target());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
 		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
-		pbdma_runlist_timeslice_timeout_128_f() |
-		pbdma_runlist_timeslice_timescale_3_f() |
-		pbdma_runlist_timeslice_enable_true_f());
+		g->ops.pbdma.get_fc_runlist_timeslice());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(ch->chid));
 
 	if (ch->is_privileged_channel) {
 		/* Set privilege level for channel */
 		nvgpu_mem_wr32(g, mem, ram_fc_config_w(),
-			pbdma_config_auth_level_privileged_f());
+			g->ops.pbdma.get_config_auth_level_privileged());
 
 		/* Enable HCE priv mode for phys mode transfer */
 		nvgpu_mem_wr32(g, mem, ram_fc_hce_ctrl_w(),
-			pbdma_hce_ctrl_hce_priv_mode_yes_f());
+			g->ops.pbdma.get_ctrl_hce_priv_mode_yes());
 	}
 
 	return g->ops.ramfc.commit_userd(ch);
@@ -134,7 +118,7 @@ u32 gp10b_ramfc_get_syncpt(struct channel_gk20a *ch)
 	u32 v, syncpt;
 
 	v = nvgpu_mem_rd32(g, &ch->inst_block, ram_fc_allowed_syncpoints_w());
-	syncpt = pbdma_allowed_syncpoints_0_index_v(v);
+	syncpt = g->ops.pbdma.allowed_syncpoints_0_index_v(v);
 
 	return syncpt;
 }
@@ -142,8 +126,8 @@ u32 gp10b_ramfc_get_syncpt(struct channel_gk20a *ch)
 void gp10b_ramfc_set_syncpt(struct channel_gk20a *ch, u32 syncpt)
 {
 	struct gk20a *g = ch->g;
-	u32 v = pbdma_allowed_syncpoints_0_valid_f(1) |
-		pbdma_allowed_syncpoints_0_index_f(syncpt);
+	u32 v = g->ops.pbdma.allowed_syncpoints_0_valid_f() |
+		g->ops.pbdma.allowed_syncpoints_0_index_f(syncpt);
 
 	nvgpu_log_info(g, "Channel %d, syncpt id %d\n", ch->chid, syncpt);
 

drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c

@@ -27,7 +27,6 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 
-#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
 
 #include "hal/fifo/ramfc_gv11b.h"
@@ -53,45 +52,33 @@ int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
 	g->ops.ramin.init_subctx_pdb(g, mem, ch->vm->pdb.mem, replayable);
 
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
-		pbdma_gp_base_offset_f(
-			u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
+		g->ops.pbdma.get_gp_base(gpfifo_base));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
-		pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
-		pbdma_gp_base_hi_limit2_f(U32(ilog2(gpfifo_entries))));
+		g->ops.pbdma.get_gp_base_hi(gpfifo_base, gpfifo_entries));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
 		ch->g->ops.pbdma.get_signature(ch->g));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
-		pbdma_pb_header_method_zero_f() |
-		pbdma_pb_header_subchannel_zero_f() |
-		pbdma_pb_header_level_main_f() |
-		pbdma_pb_header_first_true_f() |
-		pbdma_pb_header_type_inc_f());
+		g->ops.pbdma.get_fc_pb_header());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(),
-		pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) |
-		pbdma_subdevice_status_active_f() |
-		pbdma_subdevice_channel_dma_enable_f());
+		g->ops.pbdma.get_fc_subdevice());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
-		pbdma_target_eng_ctx_valid_true_f() |
-		pbdma_target_ce_ctx_valid_true_f() |
-		pbdma_target_engine_sw_f());
+		g->ops.pbdma.get_fc_target());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
 		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
-		pbdma_runlist_timeslice_timeout_128_f() |
-		pbdma_runlist_timeslice_timescale_3_f() |
-		pbdma_runlist_timeslice_enable_true_f());
+		g->ops.pbdma.get_fc_runlist_timeslice());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(ch->chid));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
-		pbdma_set_channel_info_veid_f(ch->subctx_id));
+		g->ops.pbdma.set_channel_info_veid(ch->subctx_id));
 
 	nvgpu_mem_wr32(g, mem, ram_in_engine_wfi_veid_w(),
 		ram_in_engine_wfi_veid_f(ch->subctx_id));
@@ -99,16 +86,16 @@ int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
 	if (ch->is_privileged_channel) {
 		/* Set privilege level for channel */
 		nvgpu_mem_wr32(g, mem, ram_fc_config_w(),
-			pbdma_config_auth_level_privileged_f());
+			g->ops.pbdma.get_config_auth_level_privileged());
 
 		/* Enable HCE priv mode for phys mode transfer */
 		nvgpu_mem_wr32(g, mem, ram_fc_hce_ctrl_w(),
-			pbdma_hce_ctrl_hce_priv_mode_yes_f());
+			g->ops.pbdma.get_ctrl_hce_priv_mode_yes());
 	}
 
 	/* Enable userd writeback */
 	data = nvgpu_mem_rd32(g, mem, ram_fc_config_w());
-	data = data | pbdma_config_userd_writeback_enable_f();
+	data = data | g->ops.pbdma.config_userd_writeback_enable();
 	nvgpu_mem_wr32(g, mem, ram_fc_config_w(), data);
 
 	return g->ops.ramfc.commit_userd(ch);

drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c

@@ -47,38 +47,28 @@ int tu104_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
 	nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
-		pbdma_gp_base_offset_f(
-			u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
+		g->ops.pbdma.get_gp_base(gpfifo_base));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
-		pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
-		pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
+		g->ops.pbdma.get_gp_base_hi(gpfifo_base, gpfifo_entries));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
 		g->ops.pbdma.get_signature(g));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
-		pbdma_pb_header_method_zero_f() |
-		pbdma_pb_header_subchannel_zero_f() |
-		pbdma_pb_header_level_main_f() |
-		pbdma_pb_header_first_true_f() |
-		pbdma_pb_header_type_inc_f());
+		g->ops.pbdma.get_fc_pb_header());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(),
-		pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) |
-		pbdma_subdevice_status_active_f() |
-		pbdma_subdevice_channel_dma_enable_f());
+		g->ops.pbdma.get_fc_subdevice());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
-		pbdma_target_eng_ctx_valid_true_f() |
-		pbdma_target_ce_ctx_valid_true_f() |
-		pbdma_target_engine_sw_f());
+		g->ops.pbdma.get_fc_target());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
 		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
-		pbdma_set_channel_info_veid_f(ch->subctx_id));
+		g->ops.pbdma.set_channel_info_veid(ch->subctx_id));
 
 	nvgpu_mem_wr32(g, mem, ram_in_engine_wfi_veid_w(),
 		ram_in_engine_wfi_veid_f(ch->subctx_id));
@@ -86,16 +76,16 @@ int tu104_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
 	if (ch->is_privileged_channel) {
 		/* Set privilege level for channel */
 		nvgpu_mem_wr32(g, mem, ram_fc_config_w(),
-			pbdma_config_auth_level_privileged_f());
+			g->ops.pbdma.get_config_auth_level_privileged());
 
 		/* Enable HCE priv mode for phys mode transfer */
 		nvgpu_mem_wr32(g, mem, ram_fc_hce_ctrl_w(),
-			pbdma_hce_ctrl_hce_priv_mode_yes_f());
+			g->ops.pbdma.get_ctrl_hce_priv_mode_yes());
 	}
 
 	/* Enable userd writeback */
 	data = nvgpu_mem_rd32(g, mem, ram_fc_config_w());
-	data = data | pbdma_config_userd_writeback_enable_f();
+	data = data | g->ops.pbdma.config_userd_writeback_enable();
 	nvgpu_mem_wr32(g, mem, ram_fc_config_w(), data);
 
 	return g->ops.ramfc.commit_userd(ch);

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -723,6 +723,17 @@ static const struct gpu_ops gm20b_ops = {
 		.find_for_runlist = nvgpu_pbdma_find_for_runlist,
 		.format_gpfifo_entry =
 			gm20b_pbdma_format_gpfifo_entry,
+		.get_gp_base = gm20b_pbdma_get_gp_base,
+		.get_gp_base_hi = gm20b_pbdma_get_gp_base_hi,
+		.get_fc_formats = gm20b_pbdma_get_fc_formats,
+		.get_fc_pb_header = gm20b_pbdma_get_fc_pb_header,
+		.get_fc_subdevice = gm20b_pbdma_get_fc_subdevice,
+		.get_fc_target = gm20b_pbdma_get_fc_target,
+		.get_ctrl_hce_priv_mode_yes =
+			gm20b_pbdma_get_ctrl_hce_priv_mode_yes,
+		.get_userd_aperture_mask = gm20b_pbdma_get_userd_aperture_mask,
+		.get_userd_addr = gm20b_pbdma_get_userd_addr,
+		.get_userd_hi_addr = gm20b_pbdma_get_userd_hi_addr,
 	},
 	.sync = {
 #ifdef CONFIG_TEGRA_GK20A_NVHOST

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -790,6 +790,27 @@ static const struct gpu_ops gp10b_ops = {
 		.find_for_runlist = nvgpu_pbdma_find_for_runlist,
 		.format_gpfifo_entry =
 			gm20b_pbdma_format_gpfifo_entry,
+		.get_gp_base = gm20b_pbdma_get_gp_base,
+		.get_gp_base_hi = gm20b_pbdma_get_gp_base_hi,
+		.get_fc_formats = gm20b_pbdma_get_fc_formats,
+		.get_fc_pb_header = gm20b_pbdma_get_fc_pb_header,
+		.get_fc_subdevice = gm20b_pbdma_get_fc_subdevice,
+		.get_fc_target = gm20b_pbdma_get_fc_target,
+		.get_ctrl_hce_priv_mode_yes =
+			gm20b_pbdma_get_ctrl_hce_priv_mode_yes,
+		.get_userd_aperture_mask = gm20b_pbdma_get_userd_aperture_mask,
+		.get_userd_addr = gm20b_pbdma_get_userd_addr,
+		.get_userd_hi_addr = gm20b_pbdma_get_userd_hi_addr,
+		.get_fc_runlist_timeslice =
+			gp10b_pbdma_get_fc_runlist_timeslice,
+		.get_config_auth_level_privileged =
+			gp10b_pbdma_get_config_auth_level_privileged,
+		.allowed_syncpoints_0_index_f =
+			gp10b_pbdma_allowed_syncpoints_0_index_f,
+		.allowed_syncpoints_0_valid_f =
+			gp10b_pbdma_allowed_syncpoints_0_valid_f,
+		.allowed_syncpoints_0_index_v =
+			gp10b_pbdma_allowed_syncpoints_0_index_v,
 	},
 	.sync = {
 #ifdef CONFIG_TEGRA_GK20A_NVHOST

drivers/gpu/nvgpu/hal/init/hal_gv100.c

@@ -969,6 +969,24 @@ static const struct gpu_ops gv100_ops = {
 		.find_for_runlist = nvgpu_pbdma_find_for_runlist,
 		.format_gpfifo_entry =
 			gm20b_pbdma_format_gpfifo_entry,
+		.get_gp_base = gm20b_pbdma_get_gp_base,
+		.get_gp_base_hi = gm20b_pbdma_get_gp_base_hi,
+		.get_fc_formats = NULL,
+		.get_fc_pb_header = gv11b_pbdma_get_fc_pb_header,
+		.get_fc_subdevice = gm20b_pbdma_get_fc_subdevice,
+		.get_fc_target = gv11b_pbdma_get_fc_target,
+		.get_ctrl_hce_priv_mode_yes =
+			gm20b_pbdma_get_ctrl_hce_priv_mode_yes,
+		.get_userd_aperture_mask = gm20b_pbdma_get_userd_aperture_mask,
+		.get_userd_addr = gm20b_pbdma_get_userd_addr,
+		.get_userd_hi_addr = gm20b_pbdma_get_userd_hi_addr,
+		.get_fc_runlist_timeslice =
+			gp10b_pbdma_get_fc_runlist_timeslice,
+		.get_config_auth_level_privileged =
+			gp10b_pbdma_get_config_auth_level_privileged,
+		.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
+		.config_userd_writeback_enable =
+			gv11b_pbdma_config_userd_writeback_enable,
 	},
 	.sync = {
 #ifdef CONFIG_TEGRA_GK20A_NVHOST

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -942,6 +942,24 @@ static const struct gpu_ops gv11b_ops = {
 		.find_for_runlist = nvgpu_pbdma_find_for_runlist,
 		.format_gpfifo_entry =
 			gm20b_pbdma_format_gpfifo_entry,
+		.get_gp_base = gm20b_pbdma_get_gp_base,
+		.get_gp_base_hi = gm20b_pbdma_get_gp_base_hi,
+		.get_fc_formats = NULL,
+		.get_fc_pb_header = gv11b_pbdma_get_fc_pb_header,
+		.get_fc_subdevice = gm20b_pbdma_get_fc_subdevice,
+		.get_fc_target = gv11b_pbdma_get_fc_target,
+		.get_ctrl_hce_priv_mode_yes =
+			gm20b_pbdma_get_ctrl_hce_priv_mode_yes,
+		.get_userd_aperture_mask = gm20b_pbdma_get_userd_aperture_mask,
+		.get_userd_addr = gm20b_pbdma_get_userd_addr,
+		.get_userd_hi_addr = gm20b_pbdma_get_userd_hi_addr,
+		.get_fc_runlist_timeslice =
+			gp10b_pbdma_get_fc_runlist_timeslice,
+		.get_config_auth_level_privileged =
+			gp10b_pbdma_get_config_auth_level_privileged,
+		.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
+		.config_userd_writeback_enable =
+			gv11b_pbdma_config_userd_writeback_enable,
 	},
 	.sync = {
 #ifdef CONFIG_TEGRA_GK20A_NVHOST

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1004,6 +1004,24 @@ static const struct gpu_ops tu104_ops = {
 		.find_for_runlist = nvgpu_pbdma_find_for_runlist,
 		.format_gpfifo_entry =
 			gm20b_pbdma_format_gpfifo_entry,
+		.get_gp_base = gm20b_pbdma_get_gp_base,
+		.get_gp_base_hi = gm20b_pbdma_get_gp_base_hi,
+		.get_fc_formats = NULL,
+		.get_fc_pb_header = gv11b_pbdma_get_fc_pb_header,
+		.get_fc_subdevice = gm20b_pbdma_get_fc_subdevice,
+		.get_fc_target = gv11b_pbdma_get_fc_target,
+		.get_ctrl_hce_priv_mode_yes =
+			gm20b_pbdma_get_ctrl_hce_priv_mode_yes,
+		.get_userd_aperture_mask = gm20b_pbdma_get_userd_aperture_mask,
+		.get_userd_addr = gm20b_pbdma_get_userd_addr,
+		.get_userd_hi_addr = gm20b_pbdma_get_userd_hi_addr,
+		.get_fc_runlist_timeslice =
+			gp10b_pbdma_get_fc_runlist_timeslice,
+		.get_config_auth_level_privileged =
+			gp10b_pbdma_get_config_auth_level_privileged,
+		.set_channel_info_veid = gv11b_pbdma_set_channel_info_veid,
+		.config_userd_writeback_enable =
+			gv11b_pbdma_config_userd_writeback_enable,
 	},
 	.sync = {
 #ifdef CONFIG_TEGRA_GK20A_NVHOST

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1136,6 +1136,24 @@ struct gpu_ops {
 		void (*format_gpfifo_entry)(struct gk20a *g,
 				struct nvgpu_gpfifo_entry *gpfifo_entry,
 				u64 pb_gpu_va, u32 method_size);
+		u32 (*get_gp_base)(u64 gpfifo_base);
+		u32 (*get_gp_base_hi)(u64 gpfifo_base, u32 gpfifo_entry);
+		u32 (*get_fc_formats)(void);
+		u32 (*get_fc_pb_header)(void);
+		u32 (*get_fc_subdevice)(void);
+		u32 (*get_fc_target)(void);
+		u32 (*get_ctrl_hce_priv_mode_yes)(void);
+		u32 (*get_userd_aperture_mask)(struct gk20a *g,
+				struct nvgpu_mem *mem);
+		u32 (*get_userd_addr)(u32 addr_lo);
+		u32 (*get_userd_hi_addr)(u32 addr_hi);
+		u32 (*get_fc_runlist_timeslice)(void);
+		u32 (*get_config_auth_level_privileged)(void);
+		u32 (*set_channel_info_veid)(u32 channel_id);
+		u32 (*config_userd_writeback_enable)(void);
+		u32 (*allowed_syncpoints_0_index_f)(u32 syncpt);
+		u32 (*allowed_syncpoints_0_valid_f)(void);
+		u32 (*allowed_syncpoints_0_index_v)(u32 offset);
 	} pbdma;
 
 	struct {