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gpu: nvgpu: perf: fix MISRA 10.3 violations

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MISRA Rule 10.3 prohibits assignment of objects of different essential
or narrower type. This fixes a number of MISRA 10.3 violations in
the common/perf unit.

JIRA: NVGPU-3023

Change-Id: I7edc51c62649b8e642c22ee911bc57d67b388000
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084044
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-03-28 10:53:22 -04:00
committed by mobile promotions
parent c4de71b273
commit 8efcf68017
3 changed files with 20 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/nvgpu/common/perf/cyclestats_snapshot.c
View File

@@ -68,7 +68,7 @@ bool nvgpu_css_get_overflow_status(struct gk20a *g)
u32 nvgpu_css_get_pending_snapshots(struct gk20a *g)
{
return g->ops.perf.get_membuf_pending_bytes(g) /
sizeof(struct gk20a_cs_snapshot_fifo_entry);
U32(sizeof(struct gk20a_cs_snapshot_fifo_entry));
}
/* informs hw how many snapshots have been processed (frees up fifo space) */
@@ -273,7 +273,10 @@ static int css_gr_flush_snapshots(struct channel_gk20a *ch)
/* we may have a new perfmon_id which required to */
/* switch to a new client -> let's forget current */
if (cur && !CONTAINS_PERFMON(cur, src->perfmon_id)) {
dst->put = (char *)dst_put - (char *)dst;
s64 tmp_ptr = (char *)dst_put - (char *)dst;
nvgpu_assert(tmp_ptr < (s64)U32_MAX);
dst->put = U32(tmp_ptr);
dst = NULL;
cur = NULL;
}
@@ -330,7 +333,10 @@ next_hw_fifo_entry:
/* update client put pointer if necessary */
if (cur && dst) {
dst->put = (char *)dst_put - (char *)dst;
s64 tmp_ptr = (char *)dst_put - (char *)dst;
nvgpu_assert(tmp_ptr < (s64)U32_MAX);
dst->put = U32(tmp_ptr);
}
/* re-set HW buffer after processing taking wrapping into account */
@@ -366,8 +372,8 @@ u32 nvgpu_css_allocate_perfmon_ids(struct gk20a_cs_snapshot *data,
unsigned long *pids = data->perfmon_ids;
unsigned int f;
f = bitmap_find_next_zero_area(pids, CSS_MAX_PERFMON_IDS,
CSS_FIRST_PERFMON_ID, count, 0);
f = U32(bitmap_find_next_zero_area(pids, CSS_MAX_PERFMON_IDS,
CSS_FIRST_PERFMON_ID, count, 0));
if (f > CSS_MAX_PERFMON_IDS) {
f = 0;
} else {
@@ -429,12 +435,12 @@ static int css_gr_create_client_data(struct gk20a *g,
*/
if (cur->snapshot) {
(void) memset(cur->snapshot, 0, sizeof(*cur->snapshot));
cur->snapshot->start = sizeof(*cur->snapshot);
cur->snapshot->start = U32(sizeof(*cur->snapshot));
/* we should be ensure that can fit all fifo entries here */
cur->snapshot->end =
CSS_FIFO_ENTRY_CAPACITY(cur->snapshot_size)
U32(CSS_FIFO_ENTRY_CAPACITY(cur->snapshot_size)
* sizeof(struct gk20a_cs_snapshot_fifo_entry)
+ sizeof(struct gk20a_cs_snapshot_fifo);
+ sizeof(struct gk20a_cs_snapshot_fifo));
cur->snapshot->get = cur->snapshot->start;
cur->snapshot->put = cur->snapshot->start;
}

5
drivers/gpu/nvgpu/common/perf/perf_gm20b.c
View File

@@ -74,7 +74,7 @@ void gm20b_perf_enable_membuf(struct gk20a *g, u32 size,
{
u32 addr_lo;
u32 addr_hi;
u32 inst_block_addr;
u64 inst_block_addr;
addr_lo = u64_lo32(buf_addr);
addr_hi = u64_hi32(buf_addr);
@@ -86,8 +86,9 @@ void gm20b_perf_enable_membuf(struct gk20a *g, u32 size,
inst_block_addr = nvgpu_inst_block_addr(g, inst_block) >> 12;
nvgpu_assert(inst_block_addr <= U64(U32_MAX));
nvgpu_writel(g, perf_pmasys_mem_block_r(),
perf_pmasys_mem_block_base_f(inst_block_addr) |
perf_pmasys_mem_block_base_f(U32(inst_block_addr)) |
perf_pmasys_mem_block_valid_true_f() |
nvgpu_aperture_mask(g, inst_block,
perf_pmasys_mem_block_target_sys_ncoh_f(),

5
drivers/gpu/nvgpu/common/perf/perf_gv11b.c
View File

@@ -74,7 +74,7 @@ void gv11b_perf_enable_membuf(struct gk20a *g, u32 size,
{
u32 addr_lo;
u32 addr_hi;
u32 inst_block_addr;
u64 inst_block_addr;
addr_lo = u64_lo32(buf_addr);
addr_hi = u64_hi32(buf_addr);
@@ -86,8 +86,9 @@ void gv11b_perf_enable_membuf(struct gk20a *g, u32 size,
inst_block_addr = nvgpu_inst_block_addr(g, inst_block) >> 12;
nvgpu_assert(inst_block_addr <= U64(U32_MAX));
nvgpu_writel(g, perf_pmasys_mem_block_r(),
perf_pmasys_mem_block_base_f(inst_block_addr) |
perf_pmasys_mem_block_base_f(U32(inst_block_addr)) |
perf_pmasys_mem_block_valid_true_f() |
nvgpu_aperture_mask(g, inst_block,
perf_pmasys_mem_block_target_sys_ncoh_f(),