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gpu: nvgpu: perf: fix MISRA 10.3 violations

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MISRA Rule 10.3 prohibits assignment of objects of different essential
or narrower type. This fixes a number of MISRA 10.3 violations in
the common/perf unit.

JIRA: NVGPU-3023

Change-Id: I7edc51c62649b8e642c22ee911bc57d67b388000
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084044
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-03-28 10:53:22 -04:00
committed by mobile promotions
parent c4de71b273
commit 8efcf68017
3 changed files with 20 additions and 12 deletions
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5
drivers/gpu/nvgpu/common/perf/perf_gm20b.c
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@@ -74,7 +74,7 @@ void gm20b_perf_enable_membuf(struct gk20a *g, u32 size,
{
u32 addr_lo;
u32 addr_hi;
u32 inst_block_addr;
u64 inst_block_addr;
addr_lo = u64_lo32(buf_addr);
addr_hi = u64_hi32(buf_addr);
@@ -86,8 +86,9 @@ void gm20b_perf_enable_membuf(struct gk20a *g, u32 size,
inst_block_addr = nvgpu_inst_block_addr(g, inst_block) >> 12;
nvgpu_assert(inst_block_addr <= U64(U32_MAX));
nvgpu_writel(g, perf_pmasys_mem_block_r(),
perf_pmasys_mem_block_base_f(inst_block_addr) |
perf_pmasys_mem_block_base_f(U32(inst_block_addr)) |
perf_pmasys_mem_block_valid_true_f() |
nvgpu_aperture_mask(g, inst_block,
perf_pmasys_mem_block_target_sys_ncoh_f(),