nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Add check_priv_security fuse ops

Browse Source 
-New fuse ops is added to set NVGPU_SEC_PRIVSECURITY
 and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags
 during hal initialization

-For igpu non simulation platforms, fuses are read
 to decide if gpu should be allowed to boot or not.
--Do not boot gpu if priv_sec_en is set but wpr_enabled
  is not set to 1 or vpr_auto_fetch_disable is not set to 0
--With priv_sec_en set, all falcons have to boot
  in LS mode and this needs wpr_enabled set to 1
  AND vpr_auto_fetch_disable set to 0. In this case
  gmmu tries to pull wpr and vpr settings from tegra mc

Bug 2018223

Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595454
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2017-11-09 14:13:25 -08:00
committed by mobile promotions
parent f34a4d0b12
commit 8fe633449f
18 changed files with 515 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c Normal file
View File

@@ -0,0 +1,37 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/enabled.h>
#include "gk20a/gk20a.h"
int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g)
{
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
else
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
return 0;
}

30
drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _VGPU_GM20B_FUSE
#define _VGPU_GM20B_FUSE
struct gk20a;
int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g);
#endif

22
drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
View File

@@ -24,6 +24,7 @@
#include "common/linux/vgpu/fecs_trace_vgpu.h"
#include "common/linux/vgpu/css_vgpu.h"
#include "vgpu_gr_gm20b.h"
#include "vgpu_fuse_gm20b.h"
#include "gk20a/bus_gk20a.h"
#include "gk20a/flcn_gk20a.h"
@@ -456,6 +457,9 @@ static const struct gpu_ops vgpu_gm20b_ops = {
.priv_ring = {
.isr = gk20a_priv_ring_isr,
},
.fuse = {
.check_priv_security = vgpu_gm20b_fuse_check_priv_security,
},
.chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
.get_litter_value = gm20b_get_litter_value,
};
@@ -463,7 +467,6 @@ static const struct gpu_ops vgpu_gm20b_ops = {
int vgpu_gm20b_init_hal(struct gk20a *g)
{
struct gpu_ops *gops = &g->ops;
u32 val;
gops->ltc = vgpu_gm20b_ops.ltc;
gops->ce2 = vgpu_gm20b_ops.ce2;
@@ -499,26 +502,19 @@ int vgpu_gm20b_init_hal(struct gk20a *g)
gops->priv_ring = vgpu_gm20b_ops.priv_ring;
gops->fuse = vgpu_gm20b_ops.fuse;
/* Lone functions */
gops->chip_init_gpu_characteristics =
vgpu_gm20b_ops.chip_init_gpu_characteristics;
gops->get_litter_value = vgpu_gm20b_ops.get_litter_value;
__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
} else {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (!val) {
gk20a_dbg_info("priv security is disabled in HW");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
} else {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
}
}
/* Read fuses to check if gpu needs to boot in secure/non-secure mode */
if (gops->fuse.check_priv_security(g))
return -EINVAL; /* Do not boot gpu */
/* priv security dependent ops */
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {

38
drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c Normal file
View File

@@ -0,0 +1,38 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/enabled.h>
#include "gk20a/gk20a.h"
int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g)
{
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
} else {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
}
return 0;
}

30
drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _VGPU_GP10B_FUSE
#define _VGPU_GP10B_FUSE
struct gk20a;
int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g);
#endif

27
drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -27,6 +27,7 @@
#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
#include "vgpu_gr_gp10b.h"
#include "vgpu_mm_gp10b.h"
#include "vgpu_fuse_gp10b.h"
#include "gk20a/bus_gk20a.h"
#include "gk20a/pramin_gk20a.h"
@@ -498,6 +499,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.priv_ring = {
.isr = gp10b_priv_ring_isr,
},
.fuse = {
.check_priv_security = vgpu_gp10b_fuse_check_priv_security,
},
.chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
.get_litter_value = gp10b_get_litter_value,
};
@@ -505,7 +509,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
int vgpu_gp10b_init_hal(struct gk20a *g)
{
struct gpu_ops *gops = &g->ops;
u32 val;
gops->ltc = vgpu_gp10b_ops.ltc;
gops->ce2 = vgpu_gp10b_ops.ce2;
@@ -531,6 +534,8 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
gops->priv_ring = vgpu_gp10b_ops.priv_ring;
gops->fuse = vgpu_gp10b_ops.fuse;
/* Lone Functions */
gops->chip_init_gpu_characteristics =
vgpu_gp10b_ops.chip_init_gpu_characteristics;
@@ -539,23 +544,9 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
} else if (g->is_virtual) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
} else {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (val) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
} else {
gk20a_dbg_info("priv security is disabled in HW");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
}
}
/* Read fuses to check if gpu needs to boot in secure/non-secure mode */
if (gops->fuse.check_priv_security(g))
return -EINVAL; /* Do not boot gpu */
/* priv security dependent ops */
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {