nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: CONFIG_TEGRA_ACR is supported by default

Browse Source 
TEGRA_ACR config is supposed to be enabled maxwell
onwards. Since gk20a support is no longer supported,
delete code that is not under TEGRA_ACR config

Change-Id: Id52485680bca1ceaadcb94f9603c0898c2002e02
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595437
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2017-11-09 15:32:11 -08:00
committed by mobile promotions
parent f53a0dd96b
commit f34a4d0b12
5 changed files with 0 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
View File

@@ -508,7 +508,6 @@ int vgpu_gm20b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
#ifdef CONFIG_TEGRA_ACR
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
} else {
@@ -520,21 +519,6 @@ int vgpu_gm20b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
}
}
#else
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
gk20a_dbg_info("running ASIM with PRIV security disabled");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
} else {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (!val) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
} else {
gk20a_dbg_info("priv security is not supported but enabled");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
return -EPERM;
}
}
#endif
/* priv security dependent ops */
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {

19
drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -539,7 +539,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
#ifdef CONFIG_TEGRA_ACR
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
@@ -557,24 +556,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
}
}
#else
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
gk20a_dbg_info("running simulator with PRIV security disabled");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
} else {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (val) {
gk20a_dbg_info("priv security is not supported but enabled");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
return -EPERM;
} else {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
}
}
#endif
/* priv security dependent ops */
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {

9
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -737,7 +737,6 @@ u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr)
return 0;
}
#ifdef CONFIG_TEGRA_ACR
static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
{
struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
@@ -830,14 +829,6 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
return 0;
}
#else
int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
{
return -EPERM;
}
#endif
void gr_gm20b_detect_sm_arch(struct gk20a *g)
{

16
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -634,7 +634,6 @@ int gm20b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
#ifdef CONFIG_TEGRA_ACR
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
} else {
@@ -646,21 +645,6 @@ int gm20b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
}
}
#else
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
gk20a_dbg_info("running ASIM with PRIV security disabled");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
} else {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (!val) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
} else {
gk20a_dbg_info("priv security is not supported but enabled");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
return -EPERM;
}
}
#endif
/* priv security dependent ops */
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {

19
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -662,7 +662,6 @@ int gp10b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
#ifdef CONFIG_TEGRA_ACR
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
@@ -680,24 +679,6 @@ int gp10b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
}
}
#else
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
gk20a_dbg_info("running simulator with PRIV security disabled");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
} else {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (val) {
gk20a_dbg_info("priv security is not supported but enabled");
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
return -EPERM;
} else {
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
}
}
#endif
/* priv security dependent ops */
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {