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gpu: nvgpu: fifo_gk20a: fix some declaration types

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This fixes some declarations in fifo_gk20a that resulted in MISRA 10.3
violations. MISRA 10.3 prohibits implicit assignment between types.

JIRA NVGPU-647

Change-Id: I28df83a73c5530c37275cdd36c6c56d03a1ccadd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917633
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2018-10-02 16:30:06 -04:00
committed by mobile promotions
parent 1040a3a534
commit 901cf5ffcb
2 changed files with 17 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -45,6 +45,7 @@
#include <nvgpu/utils.h> #include <nvgpu/utils.h>
#include <nvgpu/channel.h> #include <nvgpu/channel.h>
#include <nvgpu/unit.h> #include <nvgpu/unit.h>
#include <nvgpu/types.h>
#include "gk20a.h" #include "gk20a.h"
#include "mm_gk20a.h" #include "mm_gk20a.h"
@@ -695,7 +696,7 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f)
u32 i; u32 i;
size_t runlist_size; size_t runlist_size;
u32 active_engine_id, pbdma_id, engine_id; u32 active_engine_id, pbdma_id, engine_id;
int flags = nvgpu_is_enabled(g, NVGPU_MM_USE_PHYSICAL_SG) ? u32 flags = nvgpu_is_enabled(g, NVGPU_MM_USE_PHYSICAL_SG) ?
NVGPU_DMA_FORCE_CONTIGUOUS : 0; NVGPU_DMA_FORCE_CONTIGUOUS : 0;
int err = 0; int err = 0;
@@ -1895,7 +1896,7 @@ static bool gk20a_fifo_handle_mmu_fault(
return verbose; return verbose;
} }
static void gk20a_fifo_get_faulty_id_type(struct gk20a *g, int engine_id, static void gk20a_fifo_get_faulty_id_type(struct gk20a *g, u32 engine_id,
u32 *id, u32 *type) u32 *id, u32 *type)
{ {
u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id)); u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id));
@@ -2018,7 +2019,7 @@ void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids,
u32 mmu_fault_engines = 0; u32 mmu_fault_engines = 0;
u32 ref_type; u32 ref_type;
u32 ref_id; u32 ref_id;
u32 ref_id_is_tsg = false; bool ref_id_is_tsg = false;
bool id_is_known = (id_type != ID_TYPE_UNKNOWN) ? true : false; bool id_is_known = (id_type != ID_TYPE_UNKNOWN) ? true : false;
bool id_is_tsg = (id_type == ID_TYPE_TSG) ? true : false; bool id_is_tsg = (id_type == ID_TYPE_TSG) ? true : false;
u32 rlid; u32 rlid;
@@ -2244,10 +2245,10 @@ fail_enable_tsg:
} }
u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g, u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g,
int *__id, bool *__is_tsg) u32 *__id, bool *__is_tsg)
{ {
u32 engine_id; u32 engine_id;
int id = -1; u32 id = U32_MAX;
bool is_tsg = false; bool is_tsg = false;
u32 mailbox2; u32 mailbox2;
u32 active_engine_id = FIFO_INVAL_ENGINE_ID; u32 active_engine_id = FIFO_INVAL_ENGINE_ID;
@@ -2413,7 +2414,7 @@ bool gk20a_fifo_handle_sched_error(struct gk20a *g)
{ {
u32 sched_error; u32 sched_error;
u32 engine_id; u32 engine_id;
int id = -1; u32 id = U32_MAX;
bool is_tsg = false; bool is_tsg = false;
bool ret = false; bool ret = false;
@@ -2436,6 +2437,13 @@ bool gk20a_fifo_handle_sched_error(struct gk20a *g)
u32 ms = 0; u32 ms = 0;
bool verbose = false; bool verbose = false;
if (id > f->num_channels) {
nvgpu_err(g, "fifo sched error : channel id invalid %u",
id);
ret = false;
goto err;
}
if (is_tsg) { if (is_tsg) {
ret = g->ops.fifo.check_tsg_ctxsw_timeout( ret = g->ops.fifo.check_tsg_ctxsw_timeout(
&f->tsg[id], &verbose, &ms); &f->tsg[id], &verbose, &ms);

6
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -46,8 +46,8 @@ enum {
#define FIFO_INVAL_TSG_ID ((u32)~0) #define FIFO_INVAL_TSG_ID ((u32)~0)
#define FIFO_INVAL_RUNLIST_ID ((u32)~0) #define FIFO_INVAL_RUNLIST_ID ((u32)~0)
#define ID_TYPE_CHANNEL 0 #define ID_TYPE_CHANNEL 0U
#define ID_TYPE_TSG 1 #define ID_TYPE_TSG 1U
#define ID_TYPE_UNKNOWN ((u32)~0) #define ID_TYPE_UNKNOWN ((u32)~0)
#define RC_YES 1 #define RC_YES 1
@@ -285,7 +285,7 @@ u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g);
u32 gk20a_fifo_act_eng_interrupt_mask(struct gk20a *g, u32 act_eng_id); u32 gk20a_fifo_act_eng_interrupt_mask(struct gk20a *g, u32 act_eng_id);
u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g); u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g);
u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g, u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g,
int *__id, bool *__is_tsg); u32 *__id, bool *__is_tsg);
void gk20a_fifo_set_ctx_mmu_error_tsg(struct gk20a *g, void gk20a_fifo_set_ctx_mmu_error_tsg(struct gk20a *g,
struct tsg_gk20a *tsg); struct tsg_gk20a *tsg);
void gk20a_fifo_abort_tsg(struct gk20a *g, u32 tsgid, bool preempt); void gk20a_fifo_abort_tsg(struct gk20a *g, u32 tsgid, bool preempt);