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nvgpu: gpu: adds support for ACR dbg/prod.
ACR ucode is encrypted using different keys for prod/dbg boards. This change adds a check to select ACR ucode based on board type. Note: This support is added for t18x. In the sub-sequent CL, support for T210 will be added. Bug 2672836 Change-Id: Ib209f25463d05edae576cfd47b63f562cb8f61e6 Signed-off-by: deepak goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471590 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -47,12 +47,32 @@ static u32 gp10b_acr_lsf_gpccs(struct gk20a *g,
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return BIT32(lsf->falcon_id);
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}
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static void gp10b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
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{
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nvgpu_log_fn(g, " ");
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/* ACR HS ucode type & f/w name*/
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hs_acr->acr_type = ACR_DEFAULT;
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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hs_acr->acr_fw_name = HSBIN_ACR_PROD_UCODE;
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} else {
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hs_acr->acr_fw_name = HSBIN_ACR_DBG_UCODE;
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}
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/* set on which falcon ACR need to execute*/
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hs_acr->acr_flcn = g->pmu->flcn;
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hs_acr->acr_engine_bus_err_status =
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g->ops.pmu.bar0_error_status;
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}
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void nvgpu_gp10b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
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{
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nvgpu_log_fn(g, " ");
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/* inherit the gm20b config data */
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nvgpu_gm20b_acr_sw_init(g, acr);
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gp10b_acr_default_sw_init(g, &acr->acr);
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/* gp10b supports LSF gpccs bootstrap */
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acr->lsf_enable_mask |= gp10b_acr_lsf_gpccs(g,
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