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gpu: nvgpu: Correct the device info table parsing

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We parse the DEVICE_INFO table entries to get IOCTRL(NVLINK)
engine related information like the pri_base_addr, reset_enum,
and the intr_enum.

For grouping the chained entries per IP, the current parsing logic
relies on the fact that engine_type entry for an IP will be parsed
before other entries in the chained group.
As the enum_type entry (which contains the reset_enum) appears
ahead of the engine_type entry, the parsing logic fails and we read
reset_enum as 0.
Modify the parsing logic to group the chained entries correctly.

Also we were using a wrong API to extract the reset/intr_enum from the
table entry.

JIRA NVGPU-966

Change-Id: I68052db5d1c88a15e04f311486f3f639caf9ed9e
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796808
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2018-08-10 16:03:14 +05:30
committed by mobile promotions
parent 4940f4c1b4
commit 90f268963c
1 changed files with 31 additions and 51 deletions
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82
drivers/gpu/nvgpu/gv100/nvlink_gv100.c
View File

@@ -2115,9 +2115,10 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
struct nvgpu_nvlink_ioctrl_list *ioctrl_table;
u32 table_entry;
u32 devinfo_type;
bool is_ioctrl = false;
bool is_chain = false;
u32 io_num_entries = 0;
u32 entry_engine = 0;
u32 entry_enum = 0;
u32 entry_data = 0;
ioctrl_table = nvgpu_kzalloc(g, top_device_info__size_1_v() *
sizeof(struct nvgpu_nvlink_ioctrl_list));
@@ -2126,64 +2127,44 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
nvgpu_err(g, "failed to allocate memory for nvlink io table");
return -ENOMEM;
}
for (i = 0; i < top_device_info__size_1_v(); i++) {
table_entry = gk20a_readl(g, top_device_info_r(i));
nvgpu_log(g, gpu_dbg_nvlink, "Table entry: 0x%x", table_entry);
devinfo_type = top_device_info_entry_v(table_entry);
if (devinfo_type == top_device_info_entry_not_valid_v())
if (devinfo_type == top_device_info_entry_not_valid_v()) {
nvgpu_log(g, gpu_dbg_nvlink, "Invalid entry");
continue;
}
if (devinfo_type == top_device_info_entry_engine_type_v()) {
if (top_device_info_type_enum_v(table_entry) ==
top_device_info_type_enum_ioctrl_v())
is_ioctrl = true;
else {
is_ioctrl = false;
continue;
}
entry_engine = table_entry;
} else if (devinfo_type == top_device_info_entry_data_v()) {
entry_data = table_entry;
} else if (devinfo_type == top_device_info_entry_enum_v()) {
entry_enum = table_entry;
}
if (top_device_info_chain_v(table_entry) !=
top_device_info_chain_enable_v())
break;
if (top_device_info_chain_v(table_entry) ==
top_device_info_chain_enable_v()) {
continue;
}
is_chain = true;
if (top_device_info_type_enum_v(entry_engine) ==
top_device_info_type_enum_ioctrl_v()) {
nvgpu_log(g, gpu_dbg_nvlink, "IOCTRL entries");
nvgpu_log(g, gpu_dbg_nvlink,
" enum: 0x%x, engine = 0x%x, data = 0x%x",
entry_enum, entry_engine, entry_data);
ioctrl_table[io_num_entries].valid = true;
continue;
}
if (devinfo_type == top_device_info_entry_data_v()) {
if (is_ioctrl && is_chain) {
ioctrl_table[io_num_entries].pri_base_addr =
top_device_info_data_pri_base_v(table_entry) <<
top_device_info_data_pri_base_align_v();
if (top_device_info_chain_v(table_entry) !=
top_device_info_chain_enable_v()) {
is_chain = false;
io_num_entries++;
}
}
continue;
}
if (devinfo_type == top_device_info_entry_enum_v()) {
if (is_ioctrl && is_chain) {
ioctrl_table[io_num_entries].intr_enum =
top_device_info_intr_v(table_entry);
ioctrl_table[io_num_entries].reset_enum =
top_device_info_reset_v(table_entry);
if (top_device_info_chain_v(table_entry) !=
top_device_info_chain_enable_v()) {
is_chain = false;
io_num_entries++;
}
}
continue;
ioctrl_table[io_num_entries].intr_enum =
top_device_info_intr_enum_v(entry_enum);
ioctrl_table[io_num_entries].reset_enum =
top_device_info_reset_enum_v(entry_enum);
ioctrl_table[io_num_entries].pri_base_addr =
top_device_info_data_pri_base_v(entry_data) <<
top_device_info_data_pri_base_align_v();
io_num_entries++;
}
}
@@ -2196,7 +2177,6 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
g->nvlink.ioctrl_table = ioctrl_table;
g->nvlink.io_num_entries = io_num_entries;
for (i =0; i < io_num_entries; i++)
nvgpu_log(g, gpu_dbg_nvlink,
"Device %d : Pri Base Addr = 0x%0x Intr = %d Reset = %d",