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gpu: nvgpu: gp10b: Set address check mode

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Set address check mode for SM.

Bug 1625763

Change-Id: I5ddf8334673b414956e57c55aaa5be1a9f9aeaf1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752139
This commit is contained in:
Terje Bergstrom
2015-06-02 20:04:18 -07:00
committed by Deepak Nibade
parent 477ca4b648
commit 910bb6ad0d
2 changed files with 24 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -905,12 +905,24 @@ static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(),
gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) |
gr_pd_ab_dist_cfg2_state_limit_f(data), patch);
}
static int gr_gp10b_init_fs_state(struct gk20a *g)
{
u32 data;
data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r());
data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(),
gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
return gr_gm20b_ctx_state_floorsweep(g);
}
void gp10b_init_gr(struct gpu_ops *gops)
{
gm20b_init_gr(gops);
gops->gr.init_fs_state = gr_gp10b_init_fs_state;
gops->gr.is_valid_class = gr_gp10b_is_valid_class;
gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager;
gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool;

12
drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
View File

@@ -3758,4 +3758,16 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
{
return 0x0;
}
static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
{
return 0x00419c84;
}
static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
{
return (v & 0x7) << 8;
}
static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
{
return 0x100;
}
#endif