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gpu: nvgpu: ga10b: correct cbc base/top reg value

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CBC base and top values need to be left shifted by cbc_alignment factor
to store in the CBC_BASE and CBC_TOP registers respectively. Fix cbc
calculations accordingly.
Update cbc information debug prints to print with gpu_dbg_info flag.

Bug 3353418

Change-Id: I858c46a9dab1e5f810cabb327ba1797f15a2960e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2574119
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2021-08-10 16:31:34 -07:00
committed by mobile promotions
parent 342da8158a
commit 913a2d519f
3 changed files with 22 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c
View File

@@ -142,15 +142,16 @@ int ga10b_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc)
cbc->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice;
cbc->compbit_backing_size = compbit_backing_size;
nvgpu_log(g, gpu_dbg_pte, "supported LTCs: 0x%x",
nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte, "supported LTCs: 0x%x",
nvgpu_ltc_get_ltc_count(g));
nvgpu_log(g, gpu_dbg_pte, "ltc_count used for calculations: 0x%x",
ltc_count);
nvgpu_log(g, gpu_dbg_pte, "compbit backing store size : 0x%x",
compbit_backing_size);
nvgpu_log(g, gpu_dbg_pte, "max comptag lines: %d",
max_comptag_lines);
nvgpu_log(g, gpu_dbg_pte, "gobs_per_comptagline_per_slice: %d",
nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte,
"ltc_count used for calculations: 0x%x", ltc_count);
nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte,
"compbit backing store size : 0x%x", compbit_backing_size);
nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte,
"max comptag lines: %d", max_comptag_lines);
nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte,
"gobs_per_comptagline_per_slice: %d",
cbc->gobs_per_comptagline_per_slice);
return 0;

18
drivers/gpu/nvgpu/hal/fb/fb_ga10b.c
View File

@@ -38,22 +38,24 @@
#ifdef CONFIG_NVGPU_COMPRESSION
void ga10b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u64 base_divisor;
u64 compbit_store_base;
u64 compbit_store_pa;
u64 combit_top_size;
u64 combit_top;
u32 cbc_max_rval;
/* Unlike dgpu, partition swizzling is disabled for ga10b */
u32 num_swizzled_ltcs = 1U;
/*
* Update CBC registers
* Note: CBC Base value should be updated after CBC MAX
*/
base_divisor = g->ops.cbc.get_base_divisor(g);
combit_top_size = cbc->compbit_backing_size;
combit_top_size = round_up(combit_top_size, base_divisor);
nvgpu_assert(combit_top_size < U64(U32_MAX));
combit_top = (combit_top_size / num_swizzled_ltcs) >>
fb_mmu_cbc_top_alignment_shift_v();
nvgpu_assert(combit_top < U64(U32_MAX));
nvgpu_writel(g, fb_mmu_cbc_top_r(),
fb_mmu_cbc_top_address_f(U32(combit_top_size)));
fb_mmu_cbc_top_size_f(u64_lo32(combit_top)));
cbc_max_rval = nvgpu_readl(g, fb_mmu_cbc_max_r());
cbc_max_rval = set_field(cbc_max_rval,
@@ -62,11 +64,11 @@ void ga10b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
nvgpu_writel(g, fb_mmu_cbc_max_r(), cbc_max_rval);
compbit_store_pa = nvgpu_mem_get_addr(g, &cbc->compbit_store.mem);
compbit_store_base = round_down(compbit_store_pa, base_divisor);
compbit_store_base = (compbit_store_pa / num_swizzled_ltcs) >>
fb_mmu_cbc_base_alignment_shift_v();
nvgpu_assert(compbit_store_base < U64(U32_MAX));
nvgpu_writel(g, fb_mmu_cbc_base_r(),
fb_mmu_cbc_base_address_f(U32(compbit_store_base)));
fb_mmu_cbc_base_address_f(u64_lo32(compbit_store_base)));
nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
"compbit top size: 0x%x,%08x \n",

4
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h
View File

@@ -284,9 +284,11 @@
#define fb_mmu_cbc_max_safe_m() (U32(0x1U) << 31U)
#define fb_mmu_cbc_max_safe_true_f() (0x80000000U)
#define fb_mmu_cbc_base_r() (0x00100ec4U)
#define fb_mmu_cbc_base_alignment_shift_v() (0x0000000bU)
#define fb_mmu_cbc_base_address_f(v) ((U32(v) & 0x3ffffffU) << 0U)
#define fb_mmu_cbc_top_r() (0x00100ec8U)
#define fb_mmu_cbc_top_address_f(v) ((U32(v) & 0x7fffU) << 0U)
#define fb_mmu_cbc_top_alignment_shift_v() (0x0000000bU)
#define fb_mmu_cbc_top_size_f(v) ((U32(v) & 0x7fffU) << 0U)
#define fb_mmu_vpr_mode_r() (0x001fa800U)
#define fb_mmu_vpr_mode_fetch_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_vpr_mode_fetch_false_v() (0x00000000U)