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gpu: nvgpu: vgpu: move TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE to constants

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Also removed deprecated TEGRA_VGPU_ATTRIB_*, but leave a place holder
in case someone wants to use this command in future.

Jira VFND-3796

Change-Id: Ic36a59db238d276b0e3dd68a9d8ec5834a04333d
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1457497
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Richard Zhao
2017-04-06 17:56:08 -07:00
committed by mobile promotions
parent 40ca7cc573
commit 914bb78a7d
2 changed files with 5 additions and 30 deletions
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8
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
View File

@@ -309,6 +309,7 @@ static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
{ {
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
int err; int err;
gk20a_dbg_fn(""); gk20a_dbg_fn("");
@@ -317,11 +318,10 @@ static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
if (err) if (err)
return err; return err;
vgpu_get_attribute(vgpu_get_handle(g), g->gr.t18x.ctx_vars.preempt_image_size =
TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE, priv->constants.preempt_ctx_size;
&g->gr.t18x.ctx_vars.preempt_image_size);
if (!g->gr.t18x.ctx_vars.preempt_image_size) if (!g->gr.t18x.ctx_vars.preempt_image_size)
return -ENXIO; return -EINVAL;
return 0; return 0;
} }

27
include/linux/tegra_vgpu.h
View File

@@ -114,32 +114,6 @@ struct tegra_vgpu_channel_hwctx_params {
u64 handle; u64 handle;
}; };
enum {
TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */
TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */
TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */
TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, /* deprecated */
TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */
TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, /* deprecated */
TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, /* deprecated */
TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */
TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */
TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */
TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */
TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE = 64, /* gap to hide T18x IP */
};
struct tegra_vgpu_attrib_params { struct tegra_vgpu_attrib_params {
u32 attrib; u32 attrib;
u32 value; u32 value;
@@ -458,6 +432,7 @@ struct tegra_vgpu_constants_params {
u32 hwpm_ctx_size; u32 hwpm_ctx_size;
u8 force_preempt_mode; u8 force_preempt_mode;
u32 default_timeslice_us; u32 default_timeslice_us;
u32 preempt_ctx_size;
}; };
struct tegra_vgpu_channel_cyclestats_snapshot_params { struct tegra_vgpu_channel_cyclestats_snapshot_params {