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gpu: nvgpu: remove ZBC save/restore by PMU

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- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
  ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
  feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
  for GP10B
- Updated the GP10B PMU app version for the ucode:
  https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260

P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520

Bug 3233071
Bug 200696431

Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2476259
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Divya Singhatwaria
2021-01-27 21:35:32 +05:30
committed by mobile promotions
parent 7882f15ff6
commit 9170f2b77c
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/nvgpu/common/pmu/pmu_fw.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@
#define APP_VERSION_GV11B 25005711U
#define APP_VERSION_GV10X 23647491U
#define APP_VERSION_GP10X 24076634U
#define APP_VERSION_GP10B 23782727U
#define APP_VERSION_GP10B 29594520U
#define APP_VERSION_GM20B 20490253U
/* PMU version specific functions */
@@ -1155,7 +1155,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
set_perfmon_cntr_group_id_v2;
g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
g->pmu_ver_cmd_id_zbc_table_update = 16;
__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, false);
g->ops.pmu_ver.get_pmu_cmdline_args_size =
pmu_cmdline_size_v4;
g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =