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gpu: nvgpu: add safety build flag CONFIG_NVGPU_SW_SEMAPHORE

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Added the safety build flag CONFIG_NVGPU_SW_SEMAPHORE to compile out
sw semaphore implementation in NVGPU. sw semaphore is only used for
presilicon bringup of GPU and hence is not needed for safety build.

Jira NVGPU-3172

Change-Id: I6a46ef22f1e2059437f710198f4ea49a47656fef
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2164216
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2019-07-30 15:39:48 +05:30
committed by mobile promotions
parent feb3ba3d59
commit 92d009e796
14 changed files with 50 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/fifo/channel.c
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@@ -1718,6 +1718,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force)
}
nvgpu_mutex_release(&ch->sync_lock);
#ifdef CONFIG_NVGPU_SW_SEMAPHORE
/*
* free the channel used semaphore index.
* we need to do this before releasing the address space,
@@ -1726,6 +1727,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force)
if (ch->hw_sema != NULL) {
nvgpu_hw_semaphore_free(ch);
}
#endif
/*
* When releasing the channel we unbind the VM - so release the ref.
@@ -2739,7 +2741,9 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g,
for (chid = 0U; chid < f->num_channels; chid++) {
struct nvgpu_channel *ch = &f->channel[chid];
struct nvgpu_channel_dump_info *info = infos[chid];
#ifdef CONFIG_NVGPU_SW_SEMAPHORE
struct nvgpu_hw_semaphore *hw_sema = ch->hw_sema;
#endif
/* if this info exists, the above loop took a channel ref */
if (info == NULL) {
@@ -2752,12 +2756,14 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g,
info->refs = nvgpu_atomic_read(&ch->ref_count);
info->deterministic = ch->deterministic;
#ifdef CONFIG_NVGPU_SW_SEMAPHORE
if (hw_sema != NULL) {
info->sema.value = nvgpu_hw_semaphore_read(hw_sema);
info->sema.next =
(u32)nvgpu_hw_semaphore_read_next(hw_sema);
info->sema.addr = nvgpu_hw_semaphore_addr(hw_sema);
}
#endif
g->ops.channel.read_state(g, ch, &info->hw_state);
g->ops.ramfc.capture_ram_dump(g, ch, info);