nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: reduce code complexity in gr.falcon unit

Browse Source 
Reduce code complexity of following functions in gr.falcon unit
gm20b_gr_falcon_ctx_wait_ucode(complexity : 21 to 9)

Create sub functions by moving the control statement codes from the
function which has high complexity above 10.

Create two sub functions from gm20b_gr_falcon_ctx_wait_ucode function
Sub functions to check the opcode failure and opcode success.
gm20b_gr_falcon_check_ctx_opcode_success(with complexity : 7)
gm20b_gr_falcon_check_ctx_opcode_failure(with complexity : 7)
and reduce gm20b_gr_falcon_ctx_wait_ucode complexity to 9

Jira NVGPU-3662

Change-Id: I445dab4e4149af2cc88d19a5b18b105077dece5f
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165217
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2019-07-31 12:45:19 -07:00
committed by mobile promotions
parent e1e750a65a
commit feb3ba3d59
1 changed files with 87 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

158
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
View File

@@ -341,6 +341,89 @@ int gm20b_gr_falcon_wait_mem_scrubbing(struct gk20a *g)
return -ETIMEDOUT;
}
static void gm20b_gr_falcon_check_ctx_opcode_failure(struct gk20a *g,
u32 opc_fail, u32 reg,
u32 mailbox_fail, enum wait_ucode_status *check)
{
switch (opc_fail) {
case GR_IS_UCODE_OP_EQUAL:
if (reg == mailbox_fail) {
*check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_NOT_EQUAL:
if (reg != mailbox_fail) {
*check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_AND:
if ((reg & mailbox_fail) != 0U) {
*check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_LESSER:
if (reg < mailbox_fail) {
*check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_LESSER_EQUAL:
if (reg <= mailbox_fail) {
*check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_SKIP:
/* do no check on fail*/
break;
default:
nvgpu_err(g,
"invalid fail opcode 0x%x", opc_fail);
*check = WAIT_UCODE_ERROR;
break;
}
}
static void gm20b_gr_falcon_check_ctx_opcode_success(struct gk20a *g,
u32 opc_success, u32 reg,
u32 mailbox_ok, enum wait_ucode_status *check)
{
switch (opc_success) {
case GR_IS_UCODE_OP_EQUAL:
if (reg == mailbox_ok) {
*check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_NOT_EQUAL:
if (reg != mailbox_ok) {
*check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_AND:
if ((reg & mailbox_ok) != 0U) {
*check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_LESSER:
if (reg < mailbox_ok) {
*check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_LESSER_EQUAL:
if (reg <= mailbox_ok) {
*check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_SKIP:
/* do no success check */
break;
default:
nvgpu_err(g,
"invalid success opcode 0x%x", opc_success);
*check = WAIT_UCODE_ERROR;
break;
}
}
static int gm20b_gr_falcon_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
u32 *mailbox_ret, u32 opc_success,
u32 mailbox_ok, u32 opc_fail,
@@ -376,78 +459,11 @@ static int gm20b_gr_falcon_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
*mailbox_ret = reg;
}
switch (opc_success) {
case GR_IS_UCODE_OP_EQUAL:
if (reg == mailbox_ok) {
check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_NOT_EQUAL:
if (reg != mailbox_ok) {
check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_AND:
if ((reg & mailbox_ok) != 0U) {
check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_LESSER:
if (reg < mailbox_ok) {
check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_LESSER_EQUAL:
if (reg <= mailbox_ok) {
check = WAIT_UCODE_OK;
}
break;
case GR_IS_UCODE_OP_SKIP:
/* do no success check */
break;
default:
nvgpu_err(g,
"invalid success opcode 0x%x", opc_success);
gm20b_gr_falcon_check_ctx_opcode_success(g, opc_success,
reg, mailbox_ok, &check);
check = WAIT_UCODE_ERROR;
break;
}
switch (opc_fail) {
case GR_IS_UCODE_OP_EQUAL:
if (reg == mailbox_fail) {
check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_NOT_EQUAL:
if (reg != mailbox_fail) {
check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_AND:
if ((reg & mailbox_fail) != 0U) {
check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_LESSER:
if (reg < mailbox_fail) {
check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_LESSER_EQUAL:
if (reg <= mailbox_fail) {
check = WAIT_UCODE_ERROR;
}
break;
case GR_IS_UCODE_OP_SKIP:
/* do no check on fail*/
break;
default:
nvgpu_err(g,
"invalid fail opcode 0x%x", opc_fail);
check = WAIT_UCODE_ERROR;
break;
}
gm20b_gr_falcon_check_ctx_opcode_failure(g, opc_fail,
reg, mailbox_fail, &check);
if (sleepduringwait) {
nvgpu_usleep_range(delay,