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gpu: nvgpu: reduce code complexity in gr.falcon unit

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Reduce code complexity of following functions in gr.falcon unit
gv11b_gr_falcon_handle_fecs_ecc_error(complexity : 12 to 8)

Create sub functions by moving the control statement codes from
the function which has high complexity above 10.

Create one sub functions from gv11b_gr_falcon_handle_fecs_ecc_error function
One sub function to set the fecs_ecc_error status locally.
gr_falcon_set_fecs_ecc_error_status(with complexity : 5) and
reduce gv11b_gr_falcon_handle_fecs_ecc_error complexity to 8

Jira NVGPU-3662

Change-Id: I9ce3cd7b6b4fb453445457ba5f19faf7086b5fc6
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165190
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2019-07-31 11:01:18 -07:00
committed by mobile promotions
parent 3efeaf52d9
commit e1e750a65a
1 changed files with 24 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gv11b_fusa.c
View File

@@ -28,6 +28,27 @@
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
static void gr_falcon_set_fecs_ecc_error_status(u32 ecc_status,
struct nvgpu_fecs_ecc_status *fecs_ecc_status)
{
if ((ecc_status &
gr_fecs_falcon_ecc_status_corrected_err_imem_m()) != 0U) {
fecs_ecc_status->imem_corrected_err = true;
}
if ((ecc_status &
gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()) != 0U) {
fecs_ecc_status->imem_uncorrected_err = true;
}
if ((ecc_status &
gr_fecs_falcon_ecc_status_corrected_err_dmem_m()) != 0U) {
fecs_ecc_status->dmem_corrected_err = true;
}
if ((ecc_status &
gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()) != 0U) {
fecs_ecc_status->dmem_uncorrected_err = true;
}
}
void gv11b_gr_falcon_handle_fecs_ecc_error(struct gk20a *g,
struct nvgpu_fecs_ecc_status *fecs_ecc_status)
{
@@ -83,22 +104,9 @@ void gv11b_gr_falcon_handle_fecs_ecc_error(struct gk20a *g,
nvgpu_log(g, gpu_dbg_intr,
"fecs ecc interrupt intr: 0x%x", gr_fecs_intr);
if ((ecc_status &
gr_fecs_falcon_ecc_status_corrected_err_imem_m()) != 0U) {
fecs_ecc_status->imem_corrected_err = true;
}
if ((ecc_status &
gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()) != 0U) {
fecs_ecc_status->imem_uncorrected_err = true;
}
if ((ecc_status &
gr_fecs_falcon_ecc_status_corrected_err_dmem_m()) != 0U) {
fecs_ecc_status->dmem_corrected_err = true;
}
if ((ecc_status &
gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()) != 0U) {
fecs_ecc_status->dmem_uncorrected_err = true;
}
gr_falcon_set_fecs_ecc_error_status(ecc_status,
fecs_ecc_status);
if ((corrected_overflow != 0U) || (uncorrected_overflow != 0U)) {
nvgpu_info(g, "fecs ecc counter overflow!");
}