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gpu: nvgpu: ga10b: fix priv error for nvriscv bcr reg read

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Read nvriscv bcr regsiter only if priv lockdown is released.

Reading bcr during priv lockdown triggers priv violation error.

Bug 3541062

Change-Id: Ib63f1ad634a945e0f9c573b4703217dbf887a776
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2672196
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
mkumbar
2022-02-18 18:17:36 +05:30
committed by mobile promotions
parent 3da5e1515f
commit 930c218810
1 changed files with 5 additions and 5 deletions
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10
drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -79,10 +79,7 @@ void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector)
void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn) void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn)
{ {
u32 reg; u32 reg = 0;
reg = nvgpu_riscv_readl(flcn, priscv_priscv_bcr_ctrl_r());
nvgpu_falcon_dbg(flcn->g, "Bootrom Configuration: 0x%08x", reg);
reg = nvgpu_falcon_readl(flcn, falcon_falcon_hwcfg2_r()); reg = nvgpu_falcon_readl(flcn, falcon_falcon_hwcfg2_r());
nvgpu_falcon_dbg(flcn->g, "HWCFG2: 0x%08x", reg); nvgpu_falcon_dbg(flcn->g, "HWCFG2: 0x%08x", reg);
@@ -92,6 +89,9 @@ void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn)
nvgpu_falcon_dbg(flcn->g, "PRIV LOCKDOWN enabled"); nvgpu_falcon_dbg(flcn->g, "PRIV LOCKDOWN enabled");
} else { } else {
nvgpu_falcon_dbg(flcn->g, "PRIV LOCKDOWN disabled"); nvgpu_falcon_dbg(flcn->g, "PRIV LOCKDOWN disabled");
reg = nvgpu_riscv_readl(flcn, priscv_priscv_bcr_ctrl_r());
nvgpu_falcon_dbg(flcn->g, "Bootrom Configuration: 0x%08x", reg);
} }
reg = nvgpu_riscv_readl(flcn, priscv_priscv_br_retcode_r()); reg = nvgpu_riscv_readl(flcn, priscv_priscv_br_retcode_r());