gpu: nvgpu: Add support for encrypted minion bin

Minion Ucode is enabling HS Ucode Encyrption. Minion Ucode builds
will put out separate Debug-signed and Prod-signed Encrypted image
files. The driver will load prod image or debug image depending
on the setting of DEBUG fuse setting.
Add support to read the SCP_CTL_STAT register to differentiate
debug and prod boards and load correct binary accordingly.
Update the binary name to support two minion ucodes binaries in
the build.

JIRA NVLINK-283
Bug 2701677

Change-Id: I5348e9705708eeab4ce639b0721f10882d8970a7
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258097
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/nvlink/minion.c

@@ -59,8 +59,17 @@ int nvgpu_nvlink_minion_load(struct gk20a *g)
 		return 0;
 	}
 
-	/* get mem unlock ucode binary */
-	nvgpu_minion_fw = nvgpu_request_firmware(g, "minion.bin", 0);
+	/* Get minion ucode binary */
+	if (g->ops.nvlink.minion.is_debug_mode != NULL) {
+		if (g->ops.nvlink.minion.is_debug_mode(g)) {
+			nvgpu_minion_fw = nvgpu_request_firmware(g,
+							"dgpu_minion_debug.bin", 0);
+		} else {
+			nvgpu_minion_fw = nvgpu_request_firmware(g,
+							"dgpu_minion_prod.bin", 0);
+		}
+	}
+
 	if (nvgpu_minion_fw == NULL) {
 		nvgpu_err(g, "minion ucode get fail");
 		err = -ENOENT;

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1496,6 +1496,7 @@ static const struct gpu_ops tu104_ops = {
 			.enable_link_intr = gv100_nvlink_minion_enable_link_intr,
 			.falcon_isr = gv100_nvlink_minion_falcon_isr,
 			.isr = gv100_nvlink_minion_isr,
+			.is_debug_mode = tu104_nvlink_minion_is_debug_mode,
 		},
 		.intr = {
 			.common_intr_enable = gv100_nvlink_common_intr_enable,

drivers/gpu/nvgpu/hal/nvlink/minion_tu104.c

@@ -23,6 +23,7 @@
 #ifdef CONFIG_NVGPU_NVLINK
 
 #include <nvgpu/nvlink_minion.h>
+#include <nvgpu/io.h>
 
 #include "minion_gv100.h"
 #include "minion_tu104.h"
@@ -60,4 +61,12 @@ u32 tu104_nvlink_minion_get_dlcmd_ordinal(struct gk20a *g,
 	return dlcmd_ordinal;
 }
 
+bool tu104_nvlink_minion_is_debug_mode(struct gk20a *g)
+{
+	u32 reg_val;
+
+	reg_val = nvgpu_readl(g, minion_scp_ctl_stat_r());
+	return (minion_scp_ctl_stat_debug_mode_v(reg_val) != 0U);
+}
+
 #endif /* CONFIG_NVGPU_NVLINK */

drivers/gpu/nvgpu/hal/nvlink/minion_tu104.h

@@ -30,4 +30,5 @@ struct gk20a;
 
 u32 tu104_nvlink_minion_get_dlcmd_ordinal(struct gk20a *g,
 					enum nvgpu_nvlink_minion_dlcmd dlcmd);
+bool tu104_nvlink_minion_is_debug_mode(struct gk20a *g);
 #endif /* MINION_TU104_H */

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -566,6 +566,7 @@ struct gpu_ops {
 								bool enable);
 			void (*falcon_isr)(struct gk20a *g);
 			void (*isr)(struct gk20a *g);
+			bool (*is_debug_mode)(struct gk20a *g);
 		} minion;
 		struct {
 			void (*common_intr_enable)(struct gk20a *g,