nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 09:12:24 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Add multiple engine and runlist support

Browse Source 
This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
   Pascal GPU series
5) Removed hard coded engine_id logic and
   made generic way
6) Code cleanup for readability

JIRA DNVGPU-26

Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156022
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Lakshmanan M
2016-06-02 09:39:52 +05:30
committed by Deepak Nibade
parent c8569f1ebf
commit 9454529abe
15 changed files with 196 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/Makefile
View File

@@ -3,7 +3,7 @@ nvgpu-t18x := ../../../../nvgpu-t18x/drivers/gpu/nvgpu
nvgpu-y += \
$(nvgpu-t18x)/gp10b/gr_gp10b.o \
$(nvgpu-t18x)/gp10b/gr_ctx_gp10b.o \
$(nvgpu-t18x)/gp10b/ce2_gp10b.o \
$(nvgpu-t18x)/gp10b/ce_gp10b.o \
$(nvgpu-t18x)/gp10b/mc_gp10b.o \
$(nvgpu-t18x)/gp10b/fifo_gp10b.o \
$(nvgpu-t18x)/gp10b/ltc_gp10b.o \

7
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -24,7 +24,7 @@
#include "gp10b/mc_gp10b.h"
#include "gp10b/ltc_gp10b.h"
#include "gp10b/mm_gp10b.h"
#include "gp10b/ce2_gp10b.h"
#include "gp10b/ce_gp10b.h"
#include "gp10b/fb_gp10b.h"
#include "gp10b/fifo_gp10b.h"
#include "gp10b/gp10b_gating_reglist.h"
@@ -149,6 +149,9 @@ static int gp106_get_litter_value(struct gk20a *g,
case GPU_LIT_ROP_SHARED_BASE:
ret = proj_rop_shared_base_v();
break;
case GPU_LIT_HOST_NUM_ENGINES:
ret = proj_host_num_engines_v();
break;
case GPU_LIT_HOST_NUM_PBDMA:
ret = proj_host_num_pbdma_v();
break;
@@ -189,7 +192,7 @@ int gp106_init_hal(struct gk20a *g)
gp10b_init_ltc(gops);
gp10b_init_fb(gops);
gp10b_init_fifo(gops);
gp10b_init_ce2(gops);
gp10b_init_ce(gops);
gp106_init_gr_ctx(gops);
gp10b_init_mm(gops);
gp106_init_pmu_ops(gops);

18
drivers/gpu/nvgpu/gp106/hw_ce2_gp106.h → drivers/gpu/nvgpu/gp106/hw_ce_gp106.h
View File

@@ -47,34 +47,34 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ce2_gp106_h_
#define _hw_ce2_gp106_h_
#ifndef _hw_ce_gp106_h_
#define _hw_ce_gp106_h_
static inline u32 ce2_intr_status_r(u32 i)
static inline u32 ce_intr_status_r(u32 i)
{
return 0x00104410 + i*128;
}
static inline u32 ce2_intr_status_blockpipe_pending_f(void)
static inline u32 ce_intr_status_blockpipe_pending_f(void)
{
return 0x1;
}
static inline u32 ce2_intr_status_blockpipe_reset_f(void)
static inline u32 ce_intr_status_blockpipe_reset_f(void)
{
return 0x1;
}
static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
{
return 0x2;
}
static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
{
return 0x2;
}
static inline u32 ce2_intr_status_launcherr_pending_f(void)
static inline u32 ce_intr_status_launcherr_pending_f(void)
{
return 0x4;
}
static inline u32 ce2_intr_status_launcherr_reset_f(void)
static inline u32 ce_intr_status_launcherr_reset_f(void)
{
return 0x4;
}

4
drivers/gpu/nvgpu/gp106/hw_proj_gp106.h
View File

@@ -106,6 +106,10 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void)
{
return 0x00001800;
}
static inline u32 proj_host_num_engines_v(void)
{
return 0x00000009;
}
static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000004;

8
drivers/gpu/nvgpu/gp106/hw_top_gp106.h
View File

@@ -146,6 +146,14 @@ static inline u32 top_device_info_type_enum_copy0_f(void)
{
return 0x4;
}
static inline u32 top_device_info_type_enum_lce_v(void)
{
return 0x00000013;
}
static inline u32 top_device_info_type_enum_lce_f(void)
{
return 0x4c;
}
static inline u32 top_device_info_entry_v(u32 r)
{
return (r >> 0) & 0x3;

83
drivers/gpu/nvgpu/gp10b/ce2_gp10b.c
View File

@@ -1,83 +0,0 @@
/*
* GK20A Graphics Copy Engine (gr host)
*
* Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
#include "hw_ce2_gp10b.h"
#include "ce2_gp10b.h"
static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
{
gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
/* wake theads waiting in this channel */
gk20a_channel_semaphore_wakeup(g, true);
return ce2_intr_status_nonblockpipe_pending_f();
}
static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
{
gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n");
return ce2_intr_status_blockpipe_pending_f();
}
static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr)
{
gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n");
return ce2_intr_status_launcherr_pending_f();
}
static void gp10b_ce2_isr(struct gk20a *g)
{
u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0));
u32 clear_intr = 0;
gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr);
/* clear blocking interrupts: they exibit broken behavior */
if (ce2_intr & ce2_intr_status_blockpipe_pending_f())
clear_intr |= ce2_blockpipe_isr(g, ce2_intr);
if (ce2_intr & ce2_intr_status_launcherr_pending_f())
clear_intr |= ce2_launcherr_isr(g, ce2_intr);
gk20a_writel(g, ce2_intr_status_r(0), clear_intr);
return;
}
static void gp10b_ce2_nonstall_isr(struct gk20a *g)
{
u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0));
u32 clear_intr = 0;
gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f())
clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr);
gk20a_writel(g, ce2_intr_status_r(0), clear_intr);
return;
}
void gp10b_init_ce2(struct gpu_ops *gops)
{
gops->ce2.isr_stall = gp10b_ce2_isr;
gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr;
}

82
drivers/gpu/nvgpu/gp10b/ce_gp10b.c Normal file
View File

@@ -0,0 +1,82 @@
/*
* Pascal GPU series Copy Engine.
*
* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program.
*/
#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
#include "hw_ce_gp10b.h"
#include "ce_gp10b.h"
static u32 ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
{
gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n");
/* wake theads waiting in this channel */
gk20a_channel_semaphore_wakeup(g, true);
return ce_intr_status_nonblockpipe_pending_f();
}
static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
{
gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n");
return ce_intr_status_blockpipe_pending_f();
}
static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr)
{
gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n");
return ce_intr_status_launcherr_pending_f();
}
static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
{
u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
u32 clear_intr = 0;
gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
/* clear blocking interrupts: they exibit broken behavior */
if (ce_intr & ce_intr_status_blockpipe_pending_f())
clear_intr |= ce_blockpipe_isr(g, ce_intr);
if (ce_intr & ce_intr_status_launcherr_pending_f())
clear_intr |= ce_launcherr_isr(g, ce_intr);
gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
return;
}
static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
{
u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
u32 clear_intr = 0;
gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
if (ce_intr & ce_intr_status_nonblockpipe_pending_f())
clear_intr |= ce_nonblockpipe_isr(g, ce_intr);
gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
return;
}
void gp10b_init_ce(struct gpu_ops *gops)
{
gops->ce2.isr_stall = gp10b_ce_isr;
gops->ce2.isr_nonstall = gp10b_ce_nonstall_isr;
}

15
drivers/gpu/nvgpu/gp10b/ce2_gp10b.h → drivers/gpu/nvgpu/gp10b/ce_gp10b.h
View File

@@ -1,9 +1,7 @@
/*
* drivers/video/tegra/host/gk20a/fifo_gk20a.h
* Pascal GPU series Copy Engine.
*
* GK20A graphics copy engine (gr host)
*
* Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -15,15 +13,14 @@
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
* this program.
*/
#ifndef __CE2_GP10B_H__
#define __CE2_GP10B_H__
#ifndef __CE_GP10B_H__
#define __CE_GP10B_H__
#include "gk20a/channel_gk20a.h"
#include "gk20a/tsg_gk20a.h"
void gp10b_init_ce2(struct gpu_ops *gops);
void gp10b_init_ce(struct gpu_ops *gops);
#endif /*__CE2_GP10B_H__*/

9
drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
View File

@@ -188,15 +188,17 @@ static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
gk20a_dbg_info("engine type %d", engine_type);
if (engine_type == top_device_info_type_enum_graphics_v())
ret = ENGINE_GR_GK20A;
else if (engine_type == top_device_info_type_enum_lce_v())
ret = ENGINE_CE2_GK20A;
else if (engine_type == top_device_info_type_enum_lce_v()) {
/* Default assumptions - all the CE engine have separate runlist */
ret = ENGINE_ASYNC_CE_GK20A;
}
else
gk20a_err(g->dev, "unknown engine %d", engine_type);
return ret;
}
void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
u32 *inst_id, u32 *pri_base, u32 *fault_id)
{
if (top_device_info_data_type_v(table_entry) ==
@@ -226,4 +228,5 @@ void gp10b_init_fifo(struct gpu_ops *gops)
gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
}

5
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -1182,6 +1182,9 @@ static int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o)
{
struct gr_gk20a *gr = &g->gr;
u32 gr_engine_id;
gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
gk20a_readl(g, gr_status_r()));
@@ -1202,7 +1205,7 @@ static int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n",
gk20a_readl(g, gr_fecs_intr_r()));
gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
gk20a_readl(g, fifo_engine_status_r(ENGINE_GR_GK20A)));
gk20a_readl(g, fifo_engine_status_r(gr_engine_id)));
gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
gk20a_readl(g, gr_activity_0_r()));
gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",

7
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -25,7 +25,7 @@
#include "gp10b/mc_gp10b.h"
#include "gp10b/ltc_gp10b.h"
#include "gp10b/mm_gp10b.h"
#include "gp10b/ce2_gp10b.h"
#include "gp10b/ce_gp10b.h"
#include "gp10b/fb_gp10b.h"
#include "gp10b/pmu_gp10b.h"
#include "gp10b/gr_ctx_gp10b.h"
@@ -150,6 +150,9 @@ static int gp10b_get_litter_value(struct gk20a *g,
case GPU_LIT_ROP_SHARED_BASE:
ret = proj_rop_shared_base_v();
break;
case GPU_LIT_HOST_NUM_ENGINES:
ret = proj_host_num_engines_v();
break;
case GPU_LIT_HOST_NUM_PBDMA:
ret = proj_host_num_pbdma_v();
break;
@@ -219,7 +222,7 @@ int gp10b_init_hal(struct gk20a *g)
gp10b_init_ltc(gops);
gp10b_init_fb(gops);
gp10b_init_fifo(gops);
gp10b_init_ce2(gops);
gp10b_init_ce(gops);
gp10b_init_gr_ctx(gops);
gp10b_init_mm(gops);
gp10b_init_pmu_ops(gops);

20
drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h → drivers/gpu/nvgpu/gp10b/hw_ce_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -47,34 +47,34 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ce2_gp10b_h_
#define _hw_ce2_gp10b_h_
#ifndef _hw_ce_gp10b_h_
#define _hw_ce_gp10b_h_
static inline u32 ce2_intr_status_r(u32 i)
static inline u32 ce_intr_status_r(u32 i)
{
return 0x00104410 + i*128;
}
static inline u32 ce2_intr_status_blockpipe_pending_f(void)
static inline u32 ce_intr_status_blockpipe_pending_f(void)
{
return 0x1;
}
static inline u32 ce2_intr_status_blockpipe_reset_f(void)
static inline u32 ce_intr_status_blockpipe_reset_f(void)
{
return 0x1;
}
static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
{
return 0x2;
}
static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
{
return 0x2;
}
static inline u32 ce2_intr_status_launcherr_pending_f(void)
static inline u32 ce_intr_status_launcherr_pending_f(void)
{
return 0x4;
}
static inline u32 ce2_intr_status_launcherr_reset_f(void)
static inline u32 ce_intr_status_launcherr_reset_f(void)
{
return 0x4;
}

4
drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h
View File

@@ -106,6 +106,10 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void)
{
return 0x00001800;
}
static inline u32 proj_host_num_engines_v(void)
{
return 0x00000002;
}
static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000001;

57
drivers/gpu/nvgpu/gp10b/mc_gp10b.c
View File

@@ -1,7 +1,7 @@
/*
* GP20B master
*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -101,6 +101,9 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g)
irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
{
u32 mc_intr_0;
u32 engine_id_idx;
u32 active_engine_id = 0;
u32 engine_enum = ENGINE_INVAL_GK20A;
gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
@@ -108,11 +111,26 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
if (mc_intr_0 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask)
gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
if (mc_intr_0 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask
&& g->ops.ce2.isr_stall)
g->ops.ce2.isr_stall(g);
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
active_engine_id = g->fifo.active_engines_list[engine_id_idx];
if (mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) {
engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
/* GR Engine */
if (engine_enum == ENGINE_GR_GK20A) {
gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
}
/* CE Engine */
if (((engine_enum == ENGINE_GRCE_GK20A) ||
(engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
g->ops.ce2.isr_stall){
g->ops.ce2.isr_stall(g,
g->fifo.engine_info[active_engine_id].inst_id,
g->fifo.engine_info[active_engine_id].pri_base);
}
}
}
if (mc_intr_0 & mc_intr_pfifo_pending_f())
gk20a_fifo_isr(g);
if (mc_intr_0 & mc_intr_pmu_pending_f())
@@ -133,6 +151,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
{
u32 mc_intr_1;
u32 engine_id_idx;
u32 active_engine_id = 0;
u32 engine_enum = ENGINE_INVAL_GK20A;
gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
@@ -142,13 +163,27 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
if (mc_intr_1 & mc_intr_pfifo_pending_f())
gk20a_fifo_nonstall_isr(g);
if (mc_intr_1 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask)
gk20a_gr_nonstall_isr(g);
if (mc_intr_1 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask
&& g->ops.ce2.isr_nonstall)
g->ops.ce2.isr_nonstall(g);
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
active_engine_id = g->fifo.active_engines_list[engine_id_idx];
if (mc_intr_1 & g->fifo.engine_info[active_engine_id].intr_mask) {
engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
/* GR Engine */
if (engine_enum == ENGINE_GR_GK20A) {
gk20a_gr_nonstall_isr(g);
}
/* CE Engine */
if (((engine_enum == ENGINE_GRCE_GK20A) ||
(engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
g->ops.ce2.isr_nonstall) {
g->ops.ce2.isr_nonstall(g,
g->fifo.engine_info[active_engine_id].inst_id,
g->fifo.engine_info[active_engine_id].pri_base);
}
}
}
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);

9
drivers/gpu/nvgpu/gp10b/therm_gp10b.c
View File

@@ -82,13 +82,16 @@ static int gp10b_update_therm_gate_ctrl(struct gk20a *g)
{
u32 gate_ctrl;
u32 engine_id;
u32 active_engine_id = 0;
struct fifo_gk20a *f = &g->fifo;
for (engine_id = 0; engine_id < ENGINE_INVAL_GK20A; engine_id++) {
gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine_id));
for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
active_engine_id = f->active_engines_list[engine_id];
gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
gate_ctrl = set_field(gate_ctrl,
therm_gate_ctrl_eng_delay_before_m(),
therm_gate_ctrl_eng_delay_before_f(4));
gk20a_writel(g, therm_gate_ctrl_r(engine_id), gate_ctrl);
gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
}
return 0;