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gpu: nvgpu: gp10b: Fix PDE/PTE address handling

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We were dropping the part of address that span word bounary. The register
generator does not know how to real with multi-word fields, to edit things
in manually.

Bug 1646531

Change-Id: I3ef06d6dfcb0a499ed45456d165fe60c91492250
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/747468
This commit is contained in:
Terje Bergstrom
2015-05-26 16:12:19 -07:00
committed by Deepak Nibade
parent 2907e24e8b
commit 94a7c5ff2c
2 changed files with 8 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
View File

@@ -72,7 +72,7 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
}
static inline u32 gmmu_new_pde_address_sys_f(u32 v)
{
return (v & 0xffffff) << 8;
return (v & 0xfffffff) << 8;
}
static inline u32 gmmu_new_pde_address_sys_w(void)
{
@@ -164,7 +164,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
}
static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
{
return (v & 0xffffff) << 8;
return (v & 0xfffffff) << 8;
}
static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
{
@@ -200,7 +200,7 @@ static inline u32 gmmu_new_pte_valid_false_f(void)
}
static inline u32 gmmu_new_pte_address_sys_f(u32 v)
{
return (v & 0xffffff) << 8;
return (v & 0xfffffff) << 8;
}
static inline u32 gmmu_new_pte_address_sys_w(void)
{

7
drivers/gpu/nvgpu/gp10b/mm_gp10b.c
View File

@@ -171,7 +171,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
pde_v[0] |= gmmu_new_pde_aperture_video_memory_f();
pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
pde_v[0] |= gmmu_new_pde_vol_true_f();
pde_v[1] |= pte_addr >> 24;
pde = pde3_from_index(parent, i);
gk20a_mem_wr32(pde, 0, pde_v[0]);
@@ -222,12 +222,14 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small);
pde_v[2] |= gmmu_new_dual_pde_aperture_small_video_memory_f();
pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f();
pde_v[3] |= pte_addr_small >> 24;
}
if (big_valid) {
pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big);
pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f();
pde_v[0] |= gmmu_new_dual_pde_aperture_big_video_memory_f();
pde_v[1] |= pte_addr_big >> 28;
}
pde = pde0_from_index(pte, i);
@@ -269,7 +271,8 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
gmmu_new_pte_address_sys_f(*iova
>> gmmu_new_pte_address_shift_v());
pte_w[1] = gmmu_new_pte_kind_f(kind_v) |
pte_w[1] = *iova >> (24 + gmmu_new_pte_address_shift_v()) |
gmmu_new_pte_kind_f(kind_v) |
gmmu_new_pte_comptagline_f(*ctag / ctag_granularity);
if (rw_flag == gk20a_mem_flag_read_only)