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gpu: nvgpu: add runlist_busy_engines HAL

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Split out the code to check which engines on a particular runlist are
busy from gk20a_fifo_runlist_reset_engines() and make it a HAL op.
Resetting engines is common across chips but status is read from
registers.

Jira NVGPU-1309

Change-Id: I7a63a2942a9e210481822eaf85795fc17dad0dc5
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961822
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2018-11-29 14:58:11 +02:00
committed by mobile promotions
parent c965ef8dc2
commit 94d4a42d10
9 changed files with 21 additions and 5 deletions
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18
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -3125,24 +3125,32 @@ int gk20a_fifo_disable_all_engine_activity(struct gk20a *g,
return ret;
}
static void gk20a_fifo_runlist_reset_engines(struct gk20a *g, u32 runlist_id)
u32 gk20a_fifo_runlist_busy_engines(struct gk20a *g, u32 runlist_id)
{
struct fifo_gk20a *f = &g->fifo;
u32 engines = 0;
unsigned int i;
for (i = 0; i < f->num_engines; i++) {
u32 active_engine_id = g->fifo.active_engines_list[i];
u32 status = gk20a_readl(g, fifo_engine_status_r(active_engine_id));
u32 active_engine_id = f->active_engines_list[i];
u32 engine_runlist = f->engine_info[active_engine_id].runlist_id;
u32 status_reg = fifo_engine_status_r(active_engine_id);
u32 status = gk20a_readl(g, status_reg);
bool engine_busy = fifo_engine_status_engine_v(status) ==
fifo_engine_status_engine_busy_v();
if (engine_busy &&
(f->engine_info[active_engine_id].runlist_id == runlist_id)) {
if (engine_busy && engine_runlist == runlist_id) {
engines |= BIT(active_engine_id);
}
}
return engines;
}
static void gk20a_fifo_runlist_reset_engines(struct gk20a *g, u32 runlist_id)
{
u32 engines = g->ops.fifo.runlist_busy_engines(g, runlist_id);
if (engines != 0U) {
gk20a_fifo_recover(g, engines, ~(u32)0, false, false, true,
RC_TYPE_RUNLIST_UPDATE_TIMEOUT);