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gpu: nvgpu: add hal.gr.falcon hal to invalidate current_ctx

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Add new hal g->ops.gr.falcon.set_current_ctx_invalid() in hal.gr.falcon
unit to invalidate current_ctx by setting invalid flag in register
gr_fecs_current_ctx_r()

Use new hal in gr_gk20a_init_golden_ctx_image() instead of accessing the
register directly

Define the hal for all supported chips

Jira NVGPU-2961

Change-Id: I756dac505c661ea2754abdbf6934927d1b469be3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085032
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-03-29 19:56:35 +05:30
committed by mobile promotions
parent f1402db43f
commit 953820679d
9 changed files with 21 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -806,8 +806,7 @@ restore_fe_go_idle:
gr->ctx_vars.golden_image_initialized = true;
gk20a_writel(g, gr_fecs_current_ctx_r(),
gr_fecs_current_ctx_valid_false_f());
g->ops.gr.falcon.set_current_ctx_invalid(g);
clean_up:
if (err != 0) {

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
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@@ -484,6 +484,8 @@ static const struct gpu_ops gm20b_ops = {
.falcon = {
.fecs_base_addr = gm20b_gr_falcon_fecs_base_addr,
.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
.set_current_ctx_invalid =
gm20b_gr_falcon_set_current_ctx_invalid,
.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
.fecs_ctxsw_mailbox_size =
gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
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@@ -569,6 +569,8 @@ static const struct gpu_ops gp10b_ops = {
.falcon = {
.fecs_base_addr = gm20b_gr_falcon_fecs_base_addr,
.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
.set_current_ctx_invalid =
gm20b_gr_falcon_set_current_ctx_invalid,
.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
.fecs_ctxsw_mailbox_size =
gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -713,6 +713,8 @@ static const struct gpu_ops gv100_ops = {
.falcon = {
.fecs_base_addr = gm20b_gr_falcon_fecs_base_addr,
.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
.set_current_ctx_invalid =
gm20b_gr_falcon_set_current_ctx_invalid,
.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
.fecs_ctxsw_mailbox_size =
gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -672,6 +672,8 @@ static const struct gpu_ops gv11b_ops = {
.falcon = {
.fecs_base_addr = gm20b_gr_falcon_fecs_base_addr,
.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
.set_current_ctx_invalid =
gm20b_gr_falcon_set_current_ctx_invalid,
.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
.fecs_ctxsw_mailbox_size =
gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,

7
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c
View File

@@ -456,3 +456,10 @@ u32 gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size(void)
{
return gr_fecs_ctxsw_mailbox__size_1_v();
}
void gm20b_gr_falcon_set_current_ctx_invalid(struct gk20a *g)
{
nvgpu_writel(g, gr_fecs_current_ctx_r(),
gr_fecs_current_ctx_valid_false_f());
}

2
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h
View File

@@ -54,4 +54,6 @@ void gm20b_gr_falcon_load_ctxsw_ucode_boot(struct gk20a *g,
u32 reg_offset, u32 boot_entry, u32 addr_load32, u32 blocks,
u32 dst);
void gm20b_gr_falcon_set_current_ctx_invalid(struct gk20a *g);
#endif /* NVGPU_GR_FALCON_GM20B_H */

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
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@@ -559,6 +559,7 @@ struct gpu_ops {
struct {
u32 (*fecs_base_addr)(void);
u32 (*gpccs_base_addr)(void);
void (*set_current_ctx_invalid)(struct gk20a *g);
void (*dump_stats)(struct gk20a *g);
u32 (*fecs_ctxsw_mailbox_size)(void);
u32 (*get_fecs_ctx_state_store_major_rev_id)(

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
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@@ -746,6 +746,8 @@ static const struct gpu_ops tu104_ops = {
.falcon = {
.fecs_base_addr = gm20b_gr_falcon_fecs_base_addr,
.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
.set_current_ctx_invalid =
gm20b_gr_falcon_set_current_ctx_invalid,
.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
.fecs_ctxsw_mailbox_size =
gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,